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| Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Features 1/2.5-Inch CMOS Digital Image Sensor MT9E001 Refer to the latest MT9E001 data sheet on Micron's Web site: www.mircon.com/imaging Features * * * * * * * * * Table 1: Key Performance Parameters Value * * * * DigitalClarity(R) CMOS imaging technology Superior low-light performance Low dark current Simple two-wire serial interface Auto black level calibration Support for external mechanical shutter Support for external LED or Xenon flash High frame rate preview mode with arbitrary downsize scaling from maximum resolution Programmable controls: gain, frame size/rate, exposure, left-right and top-bottom image reversal, window size, and panning Data interface: parallel On-chip phase-locked loop (PLL) Bayer pattern down-size scaler Four channel shading correction (SC) Parameter Optical format Full resolution Pixel size Chief ray angle Color filter array Shutter type Applications * Digital still cameras * Cellular phones 1/2.5-inch (4:3) 3,264 x 2,448 pixels 1.75m x 1.75m 10.19 maximum RGB Bayer pattern Electronic rolling shutter (ERS) with global reset release (GRR) Input clock frequency 6-48 MHz Maximum data rate/master 96 Mbps clock Full 11 fps Frame rate resolution Video mode 30 fps Analog 2.4-3.1V (2.8V nominal) Supply Digital 1.7-1.9V (1.8V nominal) voltage I/O 1.8 or 2.8V PLL 2.4-3.1V (2.8V nominal) ADC resolution 12-bit Responsivity 0.3 V/lux-sec (at 550nm) (preliminary) Dynamic range 70dB (preliminary) SNRMAX 38.9dB (preliminary) Full 650mW (typical) Power resolution consumption Video mode 594mW (typical) Standby 45W (typical, EXTCLK disabled) Operating temperature -30C to +70C (at junction) Package 48-pin iLCC Ordering Information Table 2: Available Part Numbers Description 48-pin iLCC Part Number MT9E001I12STC PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__1.fm - Rev. C 10/06 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sensor Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Default Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Analog Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Analog Readout Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Timing and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Analog Gain Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Using Per-color or Global Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 SMIA Gain Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Micron Imaging Gain Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Gain Code Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pedestal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Integration Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 PLL Generated Master Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PLL Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Readout Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Window Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Pixel Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Column Readout Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Horizontal Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Vertical Flip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Column and Row Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Programming Restrictions when Subsampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Binning Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Shading Correction (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 The Correction Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Output Data Format (Parallel Pixel Data Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Output Data Timing (Parallel Pixel Data Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 General Purpose Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Trigger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Streaming/Standby Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Snapshot and Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001_TOC.fm - Rev. C 10/06 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2 Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Table of Contents Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Slave Address/Data Direction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Message Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Typical Serial Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Single Read from Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Sequential Read, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Sequential Read, Start from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Single Write to Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Sequential Write, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Register Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Register Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Bit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Bit Field Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Address Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Bit Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Register Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Double-Buffered Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Using grouped_parameter_hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Bad Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Changes to Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Changes to Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Embedded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Register List and Default Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Signal State during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Power on Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001_TOC.fm - Rev. C 10/06 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: 48-Pin ILCC 10x10 Package Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Typical Configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 8 Pixels in Normal and Column Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6 Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Effect of x_odd_inc=3 on Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Effect of x_odd_inc=7 on Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Pixel Readout (no skipping, x_odd_inc=1, y_odd_inc=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Pixel Readout (x_odd_inc=3, y_odd_inc=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Pixel Readout (x_odd_inc=1, y_odd_inc=3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Pixel Readout (x_odd_inc=3, y_odd_inc=3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Pixel Readout (x_odd_inc=3, y_odd_inc=1, x_bin=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Pixel Readout (x_odd_inc=3, y_odd_inc=3, x_ybin=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Pixel Readout (x_odd_inc=7, y_odd_inc=7, x_ybin=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Pixel Data Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Pixel Data Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Xenon Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 LED Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 LED Flash Enabled Following Forced Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Single Read from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Sequential Read, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Sequential Read, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Single Write to Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Sequential Write, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Changes to Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Changes to Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Changes to Gain and Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Sensor System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 CRA vs. Image Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 I/O TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 48-Pin ILCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001_LOF.fm - Rev. C 10/06 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Recommended Gain Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Frequency Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Row Address Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Register Adjustments Required for Binning Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Row Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Trigger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Streaming/STANDBY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Address Space Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 SMIA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 1: SMIA Parameter Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3: Manufacturer Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 0: SMIA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 1: SMIA Parameter Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3: Manufacturer Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 RESET_BAR and PLL in System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Signal State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Typical Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 POR Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001_LOT.fm - Rev. C 10/06 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor General Description General Description The Micron(R) Imaging MT9E001 is a 1/2.5-inch format CMOS active-pixel digital image sensor with a pixel array of 3,264H x 2,448V. It incorporates sophisticated on-chip camera functions such as windowing, mirroring, binning and skip modes, and snapshot mode. It is programmable through a simple two-wire serial interface and has very low power consumption. The MT9E001 digital image sensor features DigitalClarity(R) technology--Micron's breakthrough low-noise CMOS imaging technology that achieves near CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, power consumption, and integration advantages of CMOS. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Signal Description Signal Description Table 3 provides the signal descriptions for the MT9E001. Table 3: Name Signal Description Type Input Input Input Input Input Input Description Serial clock for access to control and status registers. Reserved for factory use. Tie to digital ground during normal operation. Asynchronous active LOW reset. When asserted, data output stops and all internal register are restored to their factory default settings. Master clock input; PLL input clock, 6-48 MHz. Reserved for factory use. Tie to digital ground during normal operation. General purpose inputs. After reset, these pads are powered down by default (it is not necessary to bond to these pads). Any of these pads can be configured for hardware control of SADDR, output enable, and shutter trigger functions. Pixel clock. Used to qualify the LINE_VALID, FRAME_VALID and DOUT[11:0] outputs. FRAME_VALID output. Qualified by PIXCLK. LINE_VALID output. Qualified by PIXCLK. Control for external mechanical shutter. Flash output. Synchronization pulse for external light source. Twelve-bit image data output. Serial data. Digital power (1.8V). Pixel array power (2.8V). Analog power (2.8V). PLL power (2.8V). I/O power supply (1.8V or 2.8V). Digital, I/O, and PLL ground. Analog ground. SCLK TEST2 RESET_BAR EXTCLK TEST GPI[3:0] PIXCLK FRAME_VALID LINE_VALID SHUTTER FLASH DOUT[11:0] SDATA VDD VAAPIX VAA VDDPLL VDDIO DGND AGND Output Output Output Output Output Output I/O Supply Supply Supply Supply Supply Supply Supply PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Signal Description Figure 1: 48-Pin ILCC 10x10 Package Pinout Diagram (Top View) EXTCLK VDDPLL DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DGND DGND 44 6 5 4 3 2 1 48 47 46 45 NC 43 42 41 40 39 38 37 36 35 34 33 32 31 DOUT7 DOUT8 DOUT9 DOUT10 DOUT11 VDDIO PIXCLK VDD SCLK SDATA RESET_BAR VDDIO 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC NC VAA AGND VAAPIX VAAPIX VAA AGND VAA NC NC NC FRAME_VALID LINE_VALID . PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. SHUTTER FLASH TEST2 DGND GPI0 GPI1 GPI2 GPI3 TEST VDD Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Typical Connections Typical Connections Figure 2 shows typical MT9E001 device connections. For low-noise operation, the MT9E001 requires separate power supplies for analog and digital. Incoming digital and analog ground conductors can be tied together next to the die. Both power supply rails should be decoupled to ground using capacitors as close as possible to the die. The use of inductance filters is not recommended on the power supplies or output signals. The MT9E001 also supports different digital core (VDD/DGND) and I/O power (VDDIO/ DGND) power domains that can be at different voltages. The PLL requires a clean power source (VDDPLL). Figure 2: Typical Configuration (connection) Analog I/O Digital Power1 Power1 Power1 VDD R3 R3 VDDIO VDDPLL VAA VAAPIX MASTER CLOCK (6-48 MHz) EXTCLK TEST2 SDATA SCLK GPI1 GPI0 GPI2 GPI3 TEST RESET_BAR DGND DOUT[11:0] PIXCLK LINE_VALID FRAME_VALID FLASH SHUTTER To Controller From Controller or pulled HIGH/LOW as Module ID3 AGND Digital Ground Analog Ground Notes: 1. Connection diagram shows only one of many possible variations for this sensor. 2. The GPI pads can configure multiple features for the sensor. 3. Recommended resistor value is 1.5K for the two-wire serial interface RPULL-UP; however, greater value may be used for slower transmission speed. 4. All inputs must be configured with VDDIO. 5. VAA and VAAPIX must be tied together. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Architecture Overview Architecture Overview The MT9E001 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip PLL to generate all internal clocks from a single master input clock running between 6 MHz and 48 MHz. The maximum pixel rate is 96 Mbps, corresponding to a physical pixel clock rate of 96 MHz. Figure 3 shows a block diagram of the sensor. Figure 3: Block Diagram Control Registers PLL Timing and Control Active-Pixel Sensor (APS ) Array GreenR/GreenB Channel G1/G2 ADC G1/G2 Analog Processing Red/Blue Channel R/B Digital Processing ADC R /B Data Out Sensor Core PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Sensor Core Description The core of the sensor is an active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the integration. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an ADC. The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (providing further data path corrections and applying digital gain). The pixel array contains optically active and light-shielded (black) pixels. The black pixels are used to provide data for on-chip offset-correction algorithms (black level control). The sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. These registers can be accessed through a two-wire serial interface. The output from the sensor is a Bayer pattern: alternate rows are a sequence of either green/red pixels or blue/green pixels. The offset and gain stages of the analog signal chain provide per-color control of the pixel data. The control registers, timing and control and digital processing functions shown in Figure 3 on page 10 are partitioned into two logical parts: * A sensor core which provides array control and data path corrections. The output of the sensor core is 12-bit parallel pixel data stream qualified by an output data clock (PIXCLK), together with LINE_VALID and FRAME_VALID signals. * Additional functionality is required to support the SMIA standard. This includes a horizontal and vertical image scaler, a limiter, a data compressor, an output FIFO. A flash output strobe is provided to allow an external Xenon or LED light source to synchronize with the sensor exposure time. Additional I/O signals support the provision of an external mechanical shutter. Pixel Array The MT9E001 image sensor array consists of a 3,382-column by 2,540-row matrix of pixels addressed by column and row. The address (column 0, row 0) represents the upper-left corner of the entire array as oriented in the output image, which is the upperright pixel, when looking at the chip. The active region in the center of the array consists of a 3,264-columns by 2,448-rows representing the default output image. It is surrounded by a boundary region (also active), and a border of shielded dark pixels. The boundary region can be used to avoid edge effects when doing color processing to achieve a 3,264 x 2,448 result image. The 4-pixel border on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 4: Pixel Color Pattern Detail (Top Right Corner) Column Readout Direction . . . Black Pixels First Clear Pixel (94,69) Row Readout Direction B G2 B G2 B ... G1 R G1 R G1 B G2 B G2 B G1 R G1 R G1 B G2 B G2 B Default Readout Order Figure 5: Imaging a Scene Lens Scene Sensor (rear view) Row Readout Order Column Readout Order Pixel (0,0) Analog Processing Analog Readout Channel The sensor core features two identical analog readout channels, as shown in Figure 3 on page 10. The readout channel consists of two gain stages, a sample-and-hold stage with black level calibration capability, and two12-bit ADCs. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Timing and Control Analog Gain Options The MT9E001 provides two mechanisms for setting the analog gain. The first uses the SMIA gain model; the second uses the traditional Micron Imaging gain model. The following sections describe both models, the mapping between the models, and the operation of the per-color and global gain control. Use of high gains can result in reduced image quality by introducing noise and by amplifying image defects or artifacts. Using Per-color or Global Gain Control The read-only analogue_gain_capability register returns a value of "1," indicating that the MT9E001 provides per-color gain control. However, the MT9E001 also provides the option of global gain control. Per-color and global gain control can be used interchangeably. A write to a global gain register is aliased as a write of the same data to the four associated color-dependent gain registers. A read from a global gain register is aliased to a read of the associated color-dependent gain registers. The read/write gain_mode register required by SMIA has no defined function in the SMIA specification. In the MT9E001 this register has no side-effects on the operation of the gain; per-color and global gain control can be used interchangeably regardless of the state of the gain_mode register. SMIA Gain Model The SMIA gain model uses the following registers to set the analog gain: * analogue_gain_code_global * analogue_gain_code_green1 * analogue_gain_code_red * analogue_gain_code_blue * analogue_gain_code_green2 The SMIA gain model requires a uniform step size between all gain settings. The analog gain is given by: ana log ue_gain_m0 x analogue_gain_code ana log ue_gain_code_ Micron Imaging Gain Model (EQ 1) The Micron Imaging gain model uses the following registers to set the analog gain: * global_gain * greenR_gain * red_gain * blue_gain * greenB_gain This gain model maps directly to the control settings applied to the gain stages of the analog signal chain. This provides a 7-bit gain stage and two2X gain stages. As a result, the step size varies depending upon whether the 2X gain stages are enabled. The analog gain is given by: gain = (< color > _ gain[8] + 1) x (< color > _ gain[7] + 1) x < color > _ gain[6 : 0] 32 (EQ 2) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description As a result of the 2X gain stages, many of the possible gain settings can be achieved in two different ways. For example, red_gain=0x02A0 provides the same gain as red_gain=0x0240 and red_gain=0x0320. The first example uses the first 2X gain stage, the second example uses no 2X gain stage and the third example uses the second 2X gain stage. In all cases, the preferred setting is the setting that enables the first 2X gain stage and not the last 2X gain stage, since this will result in lower noise. The recommended sequence is shown in Table 4. Table 4: Recommended Gain Settings Desired Gain 1-1.969 2-7.9375 8-15.875 Recommended Gain Register Setting 0x0220-0x023F 0x02A0-0x02FF 0x03C0-0x03FF Gain Code Mapping The Micron Imaging gain model maps directly to the underlying structure of the gain stages in the analog signal chain. When the SMIA gain model is used, gain codes are translated into equivalent settings in the Micron Imaging gain model. When the SMIA gain model is in use and values have been written to the analogue_gain_code_ Digital Gain Integer digital gains in the range 1-7 can be programmed. As gain is increased, image quality degrades due to the amplification of image defects. Pedestal This block adds the value from R0x301E (data_pedestal_) to the incoming pixel value. The data_pedestal register is read-only by default but can be configured to be read/write by clearing the lock_reg bit in R0x301A-B. The only way to disable the effect of the pedestal is to set the register to "0." Integration Time The integration (exposure) time of the sensor is controlled by the fine_integration_time and coarse_integration_time registers. The limits for the fine integration time are defined by: PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description (EQ 3) fine _ integration _ time _ min fine _ integration _ time (line _ length _ pck - fine _ integration _ time _ max _ margin ) The limits for the coarse integration time are defined by: (EQ 4) coarse _ integration_time_min coarse _ integration _ time ( frame _ length _ lines - coarse _ integration_time_max_margin ) The actual integration time is given by: (EQ 5) integration _ time = ((coarse _ integration _ time x line _ length _ pck ) + fine _ integration _ time ) vt _ pix _ clk _ freq _ mhz / 106 If the integration time is set larger than the frame time, the frame time will automatically be extended to accommodate the larger integration time. When the coarse_integration_time and fine_integration_time are changed simultaneously, and the change to coarse integration time has been an increase, the first output frame will be non uniformly integrated. PLL The sensor contains a PLL for timing generation and control. The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and a set of dividers to generate the output clocks. The clocking structure is shown in Figure 6. Figure 6: Clocking Structure row_ speed [ 2: 0] vt _ pix _ clk _ div PLL output clock 1 (1, 2, 4) clk_ pixel Divider 4 vt pix clk Divider 1 External input clock ext_clk_freq _mhz PLL input clock pll_ip_clk_freq PLL internal VCO frequency clk_pixel vt_pix_clk vt_sys_clk op _sys_clk EXTCLK Pre PLL Divider PLL Multiplier (m) vt sys clk Divider op sys clk Divider pre_pll_clk_ div pll_multiplier (n+1) 2 (1-64) (m) 64 (32-128) 1 op pix clk Divider op _pix_clk clk_op Divider PLL op_ pix_ clk_ div clk_op 8 row_ speed [ 10 : 8] 1 (1, 2, 4) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 6 on page 15 shows the different clocks and (in courier font) the names of the registers that contain or are used to control their values. It also shows the default setting for each divider/multiplier control register, and the range of legal values for each divider/multiplier control register. The vt and op sys clk Divider is hardwired in the design. From the diagram, the clock frequencies can be calculated as follows: Internal pixel clock used to readout the pixel array: (EQ 6) ext_clk_freq_mhz x pll_multiplier - 24 MHz x 64 clk_pixel_freq_mhz = ------------------------------------------------------------------------------------------------------------------------------ = ---------------------------------- = 192 MHz pre_pll_clk_div x vt_pix_clk_div x row_speed [2:0] 2x4x1 External pixel clock used to output the data: (EQ 7) ext_clk_freq_mhz x pll_multiplier 24 MHz x 64 clk_op_freq_mhz = ----------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 96 MHz pre_pll_clk_div x op_pix_clk_div x row_speed [10:8] 2x8x1 Internal master clock: ext_clk_freq_mhz x pll_multiplier- 24 MHz x 64 op_pix_clk_freq_mhz = ------------------------------------------------------------------------------------ = ---------------------------------- = 96 MHz pre_pll_clk_div x 8 2x8 (EQ 8) The parameter limit register space contains registers that declare the minimum and maximum allowable values for: * The frequency allowable on each clock. * The divisors that are used to control each clock. The following factors determine what are valid values, or combinations of valid values, for the divider/multiplier control registers: * The minimum/maximum frequency limits for the associated clock must be met. pll_ip_clk_freq must be in the range 2-24 MHz. Higher frequencies are preferred. PLL internal VCO frequency must be in the range 384-768 MHz. * The minimum/maximum value for the divider/multiplier must be met. Range for m: 32-128. Range for n: 0-63. Range for (n + 1): 1-64. * The op_pix_clk must never run faster than the vt_pix_clk to ensure that the output data stream is contiguous. * Given the maximum programmed line length, the minimum blanking time, the maximum image width, the available PLL divisor/multiplier values, and the require- PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description ment that the output line time (including the necessary blanking) must be output in a time equal to or less than the time defined by line_length_pck. Although the PLL VCO input frequency range is advertised as 6 MHz-48 MHz, superior performance is obtained by keeping the VCO input frequency as high as possible. The usage of the output clocks is shown below: * clk_pixel is used by the sensor core to control the timing of the pixel array. The sensor core produces one 12-bit pixel each vt_pix_clk period. The line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of the clk_pixel period. * clk_op is used to load parallel pixel data from the output FIFO. The output FIFO generates one pixel each op_pix_clk period. PLL Generated Master Clock PLL Setup The PLL divisors should be programmed while the sensor is in the software standby state. The PLL is enabled by entering the STREAMING state. STREAMING state will be entered after the VCO lock time. The VCO lock time is 100s (typical), 1ms (maximum). The effect of programming the PLL divisors whilst the sensor is in the streaming state is UNDEFINED. Table 5: Frequency Parameters Frequency fIN fPFD fVCO Equation - fextclk /(pll_n+1) fextclk * pll_m/(pll_n+1) Min (MHz) 6 2 384 Max (MHz) 48 24 768 Readout Options The sensor core supports different readout options to modify the output image. The readout can be limited to a specific window of the original pixel array. For preview modes, the sensor core supports both skipping and pixel binning in x and y directions. By changing the readout direction, the image can be flipped in the vertical and/or mirrored in the horizontal direction. Window Size The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers. The image output from the sensor core data path is controlled by these registers. The output image size is controlled by the x_output_size and y_output_size registers. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Pixel Border The default settings of the sensor provide a 3264 x 2448 image. A border of up to 4 pixels on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers and then adjusting the x_output_size and y_output_size registers accordingly. Column Readout Limitation The MT9E001 has limitations on the allowed values of x_addr_start and x_addr_end. x_addr_start needs to be a multiple of 8 in normal mode, 16 in 2X skip or binning mode and 32 in 4X skip or binning mode. Similarly x_addr_end needs to be set so the width of the window read out after taking subsampling mode into account is a multiple of 8. Readout Modes Horizontal Mirror When the horizontal_mirror bit (R0x3040[0]) is set in the read mode register, the order of pixel readout within a row is reversed, so that readout starts from x_addr_end and ends at x_addr_start. Figure 7 shows a sequence of 6 pixels being read out with horizontal_mirror=0 and horizontal_mirror=1. Changing horizontal_mirror causes the Bayer order of the output image to change; the new Bayer order is reflected in the value of the pixel_order register. Figure 7: 8 Pixels in Normal and Column Mirror Readout Modes LINE_VALID horizontal_mirror = 0 DOUT[11:0] G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0] G3[11:0] R3[11:0] horizontal_mirror = 1 DOUT[11:0] R3[11:0] G3[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] G0[11:0] R0[11:0] Vertical Flip When the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. Figure 8 on page 19 shows a sequence of six rows being read out with vertical_flip= 0 and vertical_flip=1. Changing vertical_flip causes the Bayer order of the output image to change; the new order is reflected in the value of the pixel_order register. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 8: 6 Rows in Normal and Row Mirror Readout Modes FRAME_VALID vertical_flip=0 DOUT[11:0] Row0[11:0] Row1[11:0] Row2[11:0] Row3[11:0] Row4[11:0] Row5[11:0] vertical_flip=1 DOUT[11:0] Row5[11:0] Row4[11:0] Row3[11:0] Row2[11:0] Row1[11:0] Row0[11:0] Column and Row Skip The sensor supports subsampling. Subsampling reduces the amount of data processed by the analogue signal chain in the sensor and thereby allows the frame rate to be increased. Subsampling is enabled by changing x_odd_inc and/or y_odd_inc. Values of 1, 3 and 7 are supported. Setting both of these variables to 3 reduces the amount of row and column data processed and is equivalent to the skip2 readout mode provided by earlier Micron Imaging sensors. The following figure shows a sequence of 8 columns being read out with x_odd_inc=3 and y_odd_inc=1. Figure 9: Effect of x_odd_inc=3 on Readout Sequence LINE_VALID x_odd_inc = 1 DOUT[11:0] G0 R0 G1 R1 G2 R2 G3 R3 [11:0] [11:0] [11:0] [11:0] [11:0] [11:0] [11:0] [11:0] LINE_VALID x_odd_inc = 3 DOUT[11:0] G0 R0 G2 R2 [11:0] [11:0] [11:0] [11:0] Figure 10: Effect of x_odd_inc=7 on Readout Sequence LINE_VALID x_odd_inc = 1 DOUT[11:0] G0 [11:0] R0 [11:0] G1 [11:0] R1 [11:0] G2 [11:0] ... G7 [11:0] R7 [11:0] LINE_VALID x_odd_inc = 7 DOUT[11:0] G0 [11:0] R0 [11:0] G4 [11:0] R4 [11:0] PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description A 1/16 reduction in resolution is achieved by setting both x_odd_inc and y_odd_inc to 7. This is equivalent to skip4 readout mode provided by earlier Micron Imaging sensors. Figure 10 on page 19 shows a sequence of 16 columns being read out with x_odd_inc=7 and y_odd_inc=1. The following waveform shows a sequence of data being read out with x_odd_inc=3 and y_odd_inc=1. The effect of the different subsampling settings on the pixel array readout is shown in Figures 11 through Figure 13 on page 21. Figure 11: Pixel Readout (no skipping, x_odd_inc=1, y_odd_inc=1) X incrementing Y incrementing Figure 12: Pixel Readout (x_odd_inc=3, y_odd_inc=1) X incrementing Y incrementing PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 13: Pixel Readout (x_odd_inc=1, y_odd_inc=3) X incrementing Y incrementing Figure 14: Pixel Readout (x_odd_inc=3, y_odd_inc=3) X incrementing Y incrementing Programming Restrictions when Subsampling When subsampling is enabled as a viewfinder mode, and the sensor is switched back and forth between full resolution and subsampling, it is recommended that line_length_pck be kept constant between the two modes. This allows the same integration times to be used in each mode to maintain the same brightness. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description When subsampling is enabled, it may be necessary to adjust the x_addr_end, x_addr_start and y_addr_end settings: the values for these registers are required to correspond with rows/columns that form part of the subsampling sequence. The adjustment should be made in accordance with the following rules: x_skip_factor = (x_odd_inc + 1) / 2 y_skip_factor = (y_odd_inc + 1) / 2 * x_addr_start should be a multiple of x_skip_factor*8 * (x_addr_end - x_addr_start - 1) should be a multiple of x_skip_factor*8 * (y_addr_end - y_addr_start - 1) should be a multiple of y_skip_factor*8 The number of columns/rows read out with subsampling can be found from the equation below: * columns/rows = (addr_end - addr_start + odd_inc) / skip_factor Example: The sensor is set up to give out a 640 x 480 image: * x_addr_start = 8 * x_addr_end = 647 * y_addr_start = 8 * y_addr_end = 487 To half the resolution in each direction the registers need to be reprogrammed as follows: * x_addr_start = 0 (8 is not read out in subsampling mode) * x_addr_end = 637 (adjust for new start address and end requirement) * y_addr_start = 8 (no restrictions on row starting address) * y_addr_end = 485 (adjust for end requirement) To quarter the resolution in each direction the registers need to be reprogrammed as follows: * x_addr_start = 0 * x_addr_end = 633 (adjust for new start address and end requirement) * y_addr_start = 8 (no restrictions on row starting address) * y_addr_end = 481 (adjust for end requirement) Table 6 shows the row address sequencing for normal and subsampled readout. The same sequencing applies to column addresses for subsampled readout. There are two possible subsampling sequences for the rows (because the subsampling sequence only read half of the rows) depending upon the alignment of the start address. The row address sequencing during binning is also shown. Due to the restrictions in column readout, only one subsampling sequence that meets the required x_addr_start is supported. This corresponds to the columns for start=0 in Table 6. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Table 6: Row Address Sequencing odd_inc=1 Normal start=0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Normal start=0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12,14 13,15 14,16 15,17 8,10 9,11 10,12 11,13 4,6 5,7 6,8 7,9 8 9 10 11 8,10 9,11 10,12 11,13 start=2 odd_inc=3 Binned start=0 0,2 1,3 2,4 3,5 start=2 Normal start=0 0 1 2 3 start=2 odd_inc=7 Binned start=0 0,2 1,3 2,4 3,5 start=2 Binning The sensor supports 2 x 1 and 2 x 2 analog binning which includes column binning (xbinning), and row/column binning (xy-binning). Binning has many of the same characteristics as subsampling, however: * It gathers image data from all pixels in the active window (rather than a subset of them). * It achieves superior image quality. * It avoids the aliasing artifacts that can be a characteristic side effect of subsampling. Binning is enabled by selecting the appropriate subsampling settings (x_odd_inc=3 and y_odd_inc=1 for x-binning, x_odd_inc=3 and y_odd_inc=3 for xy-binning) and setting the appropriate binning bit in read_mode (R0x3040-1). In subsampling, x_addr_end and y_addr_end may require adjustment when binning is enabled. It is the first of the two columns/rows binned together that should be the end column/row in binning, so the requirements for the end address is exactly the same as in nonbinning subsampling mode. Binning can also be enabled when the 4X subsampling mode is enabled (x_odd_inc=7 and y_odd_inc=1 for x-binning, x_odd_inc=7 and y_odd_inc=7 for xy-binning). In this mode, however, not all pixels will be used so this is not a 4X binning implementation. An implementation providing a combination of skip2 and bin2 is used to achieve 4X subsampling with better image quality. The effect of the different subsampling settings is shown in Figure 15 on page 24 and Figure 16 on page 24. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 15: Pixel Readout (x_odd_inc=3, y_odd_inc=1, x_bin=1) X incrementing Y incrementing Figure 16: Pixel Readout (x_odd_inc=3, y_odd_inc=3, x_ybin=1) X incrementing Y incrementing PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 17: Pixel Readout (x_odd_inc=7, y_odd_inc=7, x_ybin=1) X incrementing Y incrementing Binning Limitations Binning requires different sequencing of the pixel array and imposes different timing limits on the operation of the sensor. In particular, xy-binning requires two read operations from the pixel array for each line of output data, which has the effect of increasing the minimum line blanking time. The SMIA specification cannot accommodate this variation because its parameter limit registers are defined as being static. As a result, when xy-binning is enabled, some of the programming limits declared in the parameter limit registers are no longer valid. In addition, the default values for some of the manufacturer specific registers need to be reprogrammed. The recommended settings are shown in Table 7. None of these adjustments are required for x-binning. Table 7: Register Adjustments Required for Binning Mode Default (Normal Readout) 0x06AC Recommended Setting During Binning 0x0C40 Register min_line_blanking_pck Type Read-only Notes Read-only register for control software; does not affect operation of sensor. Read-only register for control software; does not affect operation of sensor. Read-only register for control software; does not affect operation of sensor. Read-only register for control software; does not affect operation of sensor. min_line_length_pck Read-only 0x0914 0x1200 fine_integration_time_min Read-only 0x056A 0x0B1A fine_integration_time_max_margin Read-only 0x03AA 0x06E6 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Table 7: Register Adjustments Required for Binning Mode (continued) Default (Normal Readout) 0x0100 0x056A Recommended Setting During Binning 0x0238 0x0B1A Register fine_correction fine_integration_time Type Read/write Read/write Notes Affects operation of sensor Normal default is minimum value Since binning also requires subsampling to be enabled, the same restrictions apply to the setting of x_addr_end and y_addr_end ("Programming Restrictions when Subsampling" on page 21). A given row n will always be binned with row n + 2 for 2X subsampling mode and row n+4 for 4X subsampling mode. Therefore, there are two candidate rows that a row can be binned with, depending upon the alignment of y_addr_start. For a given column n, there is only one other column, n_bin, that is can be binned with. Since the x_addr_start is restricted to multiple of 8 a column n will also always we binned with column n + 2 for 2X subsampling mode and column n + 4 for 4X subsampling mode. Shading Correction (SC) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The MT9E001 has an embedded shading correction module that can be programmed to counter the shading effects on each individual Red, GreenR, GreenB, and Blue color signal. The Correction Function Color dependent solutions are calibrated using the sensor, lens system, and an image of an evenly illuminated, featureless gray calibration field. From the resulting image the color correction functions can be derived. The correction functions can then be applied to each pixel value to equalize the response across the image as follows: P corrected (row,col)=P sensor (row,col)*f(row,col) (EQ 9) where P are the pixel values and f is the color dependent correction functions for each color channel. Each function includes a set of color dependent coefficients defined by registers R0x3600-3726. The function's origin is the center point of the function used in the calculation of the coefficients. Using an origin near the central point of symmetry of the sensor response provides the best results. The center point of the function is determined by ORIGIN_C (R0x3782) and ORIGIN_R (R0x3784) and can be used to counter an offset in the system lens from the center of the sensor array. Output Data Format (Parallel Pixel Data Interface) The sensor image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking as shown in Figure 18. The amount of horizontal blanking and vertical blanking is programmable. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in the next section. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 18: Pixel Data Timing Example P0,0 P0,1 P0,2................................P0,n-1 P0,n P1,0 P1,1 P1,2................................P1,n-1 P1,n 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 VALID IMAGE HORIZONTAL BLANKING Pm-1,0 Pm-1,1.........................Pm-1,n-1 Pm-1,n Pm,0 Pm,1.........................Pm,n-1 Pm,n 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 ................................ 00 00 00 00 00 00 ................................ 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 Output Data Timing (Parallel Pixel Data Interface) The sensor core output data is synchronized with the PIXCLK output. When LINE_VALID is HIGH, one pixel data is output on the 12-bit DOUT output every PIXCLK period. By default, the sensor master input clock (vt_pix_clk_mhz) is set up as the virtual 192 MHz clock. Hence, the output clock (op_pix_clk_mhz) is set up as half the sensor master input clock (vt_pix_clk_mhz). The rising edges on the PIXCLK signal occur onehalf of a pixel clock period after transitions on LINE_VALID, FRAME_VALID, and DOUT (Figure 19). This allows PIXCLK to be used as a clock to sample the data. PIXCLK is continuously enabled, even during the blanking periods. The sensor can be programmed to delay the PIXCLK edge relative to the DOUT transitions. This can be achieved by programming the corresponding bits in the row_speed register. The parameters P, A, and Q in Figure 20 are defined inTable 8. Figure 19: Pixel Data Timing Example LINE_VALID PIXCLK HB Valid Image Data HB DOUT[11:0] P0 (11:0) P1 (11:0) P2 (11:0) P3 (11:0) P4 (11:0) Pn-1 (11:0) Pn (11:0) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Sensor Core Description Figure 20: Row Timing and FRAME_VALID/LINE_VALID Signals FRAME_VALID LINE_VALID Number of master clocks P A Q A Q A P Table 8: Row Timing Parameters Name Pixel clock period Equation R0x3016-7[2:0] / vt_pix_clk_freq_mhz Default Timing 1 pixel clock = 5.2ns 1 Parameter PIXCLK_PERIOD S A P Q A+Q N V N * (A+Q) F Skip (subsampling) factor x_odd_inc=y_odd_inc=3, S=2 x_odd_inc=y_odd_inc=7, S=4 otherwise, S=1 Active data time (x_addr_end - x_addr_start + 1) * PIXCLK_PERIOD/S Frame start/end blanking 12 * PIXCLK_PERIOD Horizontal blanking Row time Number of rows Vertical blanking Frame valid time Total frame time Note: 3264 pixel clocks = 17.0s 12 pixel clocks = 62.5ns (line_length_pck - A) * PIXCLK_PERIOD 6558 - 3264 pixel clocks = 17.16s line_length_pck * PIXCLK_PERIOD 6558 pixel clocks = 34.16s (y_addr_end - y_addr_start + y_odd_inc)/S 2448 rows ((frame_length_lines - N) * (A+Q)) + Q - (2*P) 737,766 pixel clocks = 3.84ms (N * (A + Q)) - Q + (2*P) 16,050,714 pixel clocks = 83.60ms line_length_pck * frame_length_lines * 16,788,480 pixel clocks PIXCLK_PERIOD = 87.44ms This sensor has two internal data paths. The pixel clock used in the calculations (192 MHz) will, therefore, be twice the physical pixel clock frequency (96 MHz). The parameter P is measured in physical pixel clocks, and will therefore change for sensors with two data paths as described in Table 8. The sensor timing (Table 8) is shown in terms of pixel clock and master clock cycles (Figure 18 on page 27). The default settings for the on-chip PLL generate a 9 6MHz master input clock and pixel clock given a 24 MHz input clock to the sensor. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor General Purpose Inputs General Purpose Inputs The sensor provides four general purpose inputs; before reset they are in an unknown state. After reset, the input pads associated with these signals are powered-down by default, allowing the pads to be left disconnected/floating. The general purpose inputs are enabled by setting reset_register[8] (0x301A-B[8]). Once enabled, all four inputs must be driven to valid logic levels by external signals. The state of the general purpose inputs can be read through gpi_status (0x3026[3:0]). In addition, each of the following functions can be associated with none, one or more of the general-purpose inputs so that the function can be directly controlled by a hardware input: * output enable (see "Output Enable Control" on page 29) * SADDR (selects device address for the two-wire serial interface) * trigger (see the sections below) * standby functions (see the sections below) The gpi_status register (0x3026) is used to associate a function with a general purpose input. Parallel Pixel Data Interface The parallel pixel data interface uses the following output-only signals: * FRAME_VALID * LINE_VALID * PIXCLK * DOUT[11:0] The parallel pixel data interface is disabled by default at power-up and after reset. It can be enabled by programming R0x301A. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z--this is controlled either by pin or register control, as shown in Table 9. Table 9: Output Enable Control GPI Configured OE_N Pin disabled disabled 1 X 0 Drive Signals R0x301A-B[6] 0 1 0 1 X Description Interface High-Z Interface driven Interface High-Z Interface driven Interface driven Trigger Control When the global reset feature is in use, the trigger for the sequence can be initiated either under pin or register control, as shown in Table 10 on page 30. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor General Purpose Inputs Table 10: Trigger Control GPI Configured TRIGGER in Disabled Disabled 0 X 1 Global Trigger R0x3160-1[0] 0 1 0 1 X Description Idle Trigger Idle Trigger Trigger Streaming/Standby Control The sensor can be switched between its soft standby and streaming states under pin or register control, as shown in the Table 11 above. Selection of a pin to use for the STANDBY function is described in "General Purpose Inputs" on page 29. The state diagram for transitions between soft standby and streaming states is shown in the Figure 33 on page 85. Table 11: Streaming/STANDBY GPI Configured STANDBY Pin Disabled Disabled X 0 1 Streaming R0x301A-B[2] 0 1 0 1 X Description Soft Standby Streaming Soft Standby Streaming Soft Standby Operational Modes Snapshot and Flash The sensor supports both Xenon and LED flash through the FLASH output signal. The timing of the FLASH signal with the default settings is shown in Figure 21 on page 31 through Figure 23 on page 31. The flash and flash_count registers allow the timing of the flash to be changed. The flash can be programmed to fire only once, to be delayed by a few frames when asserted, and (for Xenon flash) to program the flash duration. Enabling the LED flash will cause one bad frame, where several of the rows only have the flash on for part of their integration time. This can be avoided by forcing a restart of the frame (write reset_register[1] = 1) immediately after enabling the flash; the first bad frame will then be masked out as shown in Figure 23 on page 31. Read-only bit flash[14] is set during frames that are correctly integrated; the state of this bit is shown in Figures 21 through Figure 23 on page 31. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor General Purpose Inputs Figure 21: Xenon Flash Enabled FRAME_VALID Flash STROBE State of Triggered Bit (flash[14]) Figure 22: LED Flash Enabled FRAME_VALID Flash STROBE State of Triggered Bit (flash[14]) Flash enabled during this frame Bad frame Good frame Good frame Bad frame Flash disabled during this frame Figure 23: LED Flash Enabled Following Forced Restart FRAME_VALID Flash STROBE State of Triggered Bit (flash[14]) Flash is enabled and a restart triggered Masked out frame Good frame Good frame Masked out frame Flash disabled and a restart triggered Low Power Mode The sensor supports a low-power mode by programming register bit read_mode[9]. Setting this bit will result in the following: * Double the value of pc_speed[2:0] internally. This means halving the internal pixel clock frequency. The slower pixel clock provides more time for settling in the analog domain, thus, the low power DAC values can be approximately half the full power DAC values. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor General Purpose Inputs Enabling the low power mode will not put the sensor in subsampling mode; this has to be programmed separately as described earlier in this document. Low power is independent of the readout mode, and can also be enabled in full resolution mode. However, since the pixel clock speed is halved, the frame rates that can be achieved with low power mode are lower than in full power mode. Only internal pixel clock speeds of 1, 2 and 4 are supported; therefore, low power mode combined with pc_speed[2:0]=4 is an illegal combination. Any limitations related to changing the internal pixel clock speed will also apply to low power mode since it automatically changes the pixel clock speed. SMIA limiter registers therefore needs to be reprogram to match the new internal pixel clock frequency. Test Patterns For test purposes, pixel data can be replaced with a fixed image generated by a special test module in the pipeline. The module provides a selection of test patterns sufficient for basic testing of the signal chain. Test patterns are accessible using R0x0600 and are shown in Table 12. Table 12: Test Patterns Test Pattern Normal Operation: no test pattern Flat Field Color Bar Fade-to-Gray Color Bar Marching 1's Register Value 0 1 2 3 256 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Two-Wire Serial Interface Two-Wire Serial Interface The two-wire serial interface bus enables read/write access to control and status registers within the sensor. This interface is designed to be compatible with the "SMIA 1.0 Part2: CCP2 Specification Camera Control Interface (CCI)," that uses the electrical characteristics and transfer protocols of the two-wire serial interface specification. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD off-chip by a 1.5K resistor. Either the slave or master device can drive SDATA LOW--the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the sensor uses SCLK as an input only; therefore, never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements, as follows: * a (repeated) start condition * a slave address/data direction byte * a(an) (not) acknowledge bit * a message byte * a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a repeated start or restart condition. Stop Condition A stop condition is defined as a LOW -to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A "0" in bit [0] indicates a write, and a "1" indicates a read. The default slave addresses used by the sensor are 0x20 (write address) and 0x21 (read address), in accordance with the SMIA specification. Alternate slave addresses of 0x30 (write PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Two-Wire Serial Interface address) and 0x31 (read address) can be selected. The GPI pins can be configured for SADDR functionality through register bit fields 0x3026[6:4], and enabled by setting 0x301A[8]. These default slave addresses are also fully programmable through the I2C address registers (0x31FC-0x31FD). Before this register can be written to, it needs to be unlocked through reset_register 0x301A[3]. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. The protocol used is outside the scope of the two-wire serial interface specification and is defined as part of the SMIA CCI. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Serial Transfer A typical read or write sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a "0" indicates a write and a "1" indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a write, the master then transfers the 16-bit register address to which the write should take place. This transfer takes place as two, 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. After 8 bits have been transferred, the slave's internal register address is incremented automatically, so that the next 8 bits are written to the next register address. The master stops writing by generating a (re)start or stop condition. If the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a write request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is auto-incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a noacknowledge bit. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Two-Wire Serial Interface Single Read from Random Location This sequence (Figure 24) starts with a dummy write to the 16-bit address that is to be used for the read. The master terminates the write by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the read by generating a no-acknowledge bit followed by a stop condition. Figure 24 shows how the internal register address maintained by the sensor is loaded and incremented as the sequence proceeds. Figure 24: Single Read from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A Sr Reg Address, M Slave Address 1 A Read Data M+1 AP S = start condition P = stop condition Sr = restart condition A = acknowledge A = not-acknowledge slave to master master to slave Single Read from Current Location This sequence (Figure 25) performs a read using the current value of the sensor internal register address. The master terminates the read by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent read sequences. Figure 25: Single Read from Current Location Previous Reg Address, N S Slave Address 1 A Read Data AP S Reg Address, N+1 Slave Address 1 A Read Data N+2 AP Sequential Read, Start from Random Location This sequence (Figure 26) starts in the same way as the single read from random location (Figure 24). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte reads until "L" bytes have been read. Figure 26: Sequential Read, Start from Random Location Previous Reg Address, N Reg Address, M Slave Address 1A Read Data A M+1 S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A Sr M+1 Read Data M+2 Read Data M+3 A M+L-2 Read Data M+L-1 Read Data M+L A A AS PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Two-Wire Serial Interface Sequential Read, Start from Current Location This sequence (Figure 27) starts in the same way as the single read from current location (Figure 25 on page 35). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte reads until "L" bytes have been read. Figure 27: Sequential Read, Start from Current Location Previous Reg Address, N N+1 A Read Data A N+2 Read Data A N+L-1 Read Data N+L AS S Slave Address 1A Read Data Single Write to Random Location This sequence (Figure 28) begins with the master generating a start condition. The slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be written. The master follows this with the byte of write data. The write is terminated by the master generating a stop condition. Figure 28: Single Write to Random Location Previous Reg Address, N Reg Address, M Write Data M+1 AP A S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A Sequential Write, Start at Random Location This sequence (Figure 29) starts in the same way as the single write to random location (Figure 28). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit, and continues to perform byte writes until "L" bytes have been written. The write is terminated by the master generating a stop condition. Figure 29: Sequential Write, Start at Random Location Previous Reg Address, N Reg Address, M Write Data M+1 A S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A M+1 Write Data M+2 Write Data ......... A ......... M+L-2 Write Data M+L-1 Write Data M+L A P A A A PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Registers Registers The sensor provides a 16-bit register address space accessed through a serial interface. Each register location is 8 bits in size. The address space is divided into the five major regions shown in Table 13. Table 13: Address Space Regions Address Regions 0x0000-0x0FFF 0x1000-0x1FFF 0x2000-0x2FFF 0x3000-0x3FFF 0x4000-0xFFFF Description Configuration registers (Read-only and read-write dynamic registers) Parameter limit registers (Read-only static registers) Reserved (Undefined) Manufacturer specific registers (Read-only and read-write dynamic registers) Reserved (Undefined) Register Notation The underlying mechanism for reading and writing registers provides byte write capability. However, it is convenient to consider some registers as multiple adjacent bytes. The sensor uses 8-bit, 16-bit, and 32-bit registers; all implemented as 1 or more bytes at naturally aligned, contiguous locations in the address space. Registers are described either by address or by name. When registers are described by address, the size of the registers is explicit. For example, R0x3024 is an 8-bit register at address 0x3024, and R0x3000-1 is a 16-bit register at address 0x3000-0x3001. When registers are described by name, the size of the register is not implicit. For example, it is necessary to refer to the register table to determine that model_id is a 16-bit register. Register Aliases A consequence of the internal architecture of the sensor is that some registers are decoded at multiple addresses: some registers in configuration space are also decoded in manufacturing specific space. In order to provide unique names for all registers, the name of the register within manufacturer specific register space has a trailing underscore. For example, R0x0000-1 is model_id, and R0x3000-1 is model_id_ (see the register tables for more examples). The effect of reading or writing a register to itself or through any of its aliases is identical. Bit Fields Some registers provide control of several different pieces of related functionality and this makes it necessary to refer to bit fields within registers. As an example of the notation used for this, the least significant 4 bits of the model_id register are referred to as model_id[3:0] or R0x0000-1[3:0]. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Registers Bit Field Aliases In addition to the register aliases described above, some register fields are aliased in multiple places. For example, R0x0100 (mode_select) only has one operational bit: R0x0100[0]. This bit is aliased to R0x3001A-B[2]. The effect of reading or writing a bit field through any of its aliases is identical. Byte Ordering Registers that occupy more than one byte of address space are shown with the lowest address in the highest-order byte lane, to match the byte-ordering on the SMIA bus. For example, the model_id register is R0x0000-1. In the register table its default value is shown as 0x2B00. This means that a read from address 0x0000 would return 0x2B and a read from address 0x0001 would return 0x00. When reading this register as two 8-bit transfers on the serial interface, the 0x2B will appear on the serial interface first, followed by the 0x00. Address Alignment All register addresses are naturally-aligned: registers that occupy two bytes of address space are aligned to even 16-bit addresses, and registers that occupy four bytes of address space are aligned to 16-bit addresses that are an integer multiple of 4. Bit Representation For clarity, 32-bit hex numbers are shown with an underscore between the upper and lower sixteen bits. For example: 0x3000_01AB. Data Format Most registers represent an unsigned binary value or set of bit fields. For all other register formats, the format is stated explicitly at the start of the register description. The notation for these formats is shown in Table 14. Table 14: Data Formats Name FIX16 Description Signed fixed-point 16-bit number: two's complement number, 8 fractional bits. Examples: 0x0100 = 1.0, 0x8000 = -128, 0xFFFF = -0.0039065 Unsigned fixed-point 16-bit number: 8.8 format. Examples: 0x0100 = 1.0, 0x280 = 2.5 Example: 0x4280_0000 = 64.0 UFIX16 FLP32 Register Behavior Registers vary from "read-only," "read/write," and "read, write-1-to-clear." PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Registers Double-Buffered Registers Some sensor settings cannot be changed during frame readout. For example, changing R0x0344-5 (x_addr_start) partway through frame readout would result in inconsistent row lengths within a frame. To avoid this, the sensor double buffers many registers by implementing a "pending" and a "live" version. Reads and writes access the pending register. The live register controls the sensor operation. The value in the pending register is transferred to a live register at a fixed point in the frame timing, called frame start. Frame start is defined as the point at which the first dark row is read out internally to the sensor. By default, this occurs 82 row times before FRAME_VALID goes HIGH. R0x3044-5 enables the dark rows to be shown in the image, but this has no effect on the position of frame-start. In the register tables the "Frame Synced" field shows which registers or register fields are double-buffered in this way. Using grouped_parameter_hold The grouped_parameter_hold (R0x0104) can be used to inhibit transfers from the pending to the live registers. When the sensor is in streaming mode, this register should be written to "1" before making changes to any multi-byte registers or any group of registers where a set of changes is required to take effect simultaneously. When this register is written to "0," all transfers from pending to live registers take place on the next frame start. An example of the consequences of failing to set this bit follows: The coarse integration time is controlled by a 16-bit register. If the integration time is changed from 0x00FF to 0x0100 and the writes of 0x01, 0x00 (the two bytes used to set the new integration time) occur during a frame start, the first byte could be seen and transferred to the live register one frame sooner than the second byte. Instead of seeing successive frames integrated at 0x00FF, 0x0100, 0x0100, 0x0100, successive frames would be integrated at 0x00FF, 0x01FF, 0x0100, 0x0100. Bad Frames A bad frame is defined as a frame where all rows do not have the same integration time, or where offsets to the pixel values have changed during the frame. Many changes to the sensor register settings can cause a bad frame. For example, when line_length_pck (R0x0342-3) is changed, the new register value does not affect sensor behavior until the next frame start. However, the frame that would be read out at that frame start will have been integrated using the old row width, so reading it out using the new row width would result in a frame with an incorrect integration time. By default, bad frames are not masked. However, when bad frames are masked (0x301A[9]), LINE_VALID and FRAME_VALID are inhibited for these frames so that the vertical blanking time between frames is extended by the frame time. In the register tables, the "Cause Bad Frame" field shows where changing a register or register field will cause a bad frame. The following notation is used: * False:Changing the register value will not produce a bad frame. * True:Changing the register value might produce a bad frame. * Dropped: As true, but the bad frame will be masked out when mask_corrupted_frames (R0x0105) is set to "1." PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Registers Changes to Integration Time If the integration time is changed while FRAME_VALID is asserted for frame n, the first frame output using the new integration time is frame (n + 2). The sequence is as follows: 1. During frame n, the new integration time is held in the pending register. 2. At the start of frame (n + 1), the new integration time is transferred to the live register. Integration for each row of frame (n + 1) has been completed using the old integration time. 3. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent upon the new value of the integration time. 4. When frame (n + 1) is read out, the next frame will have been integrated using the new integration time. If the integration time is changed on successive frames, each value written will be applied for a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. Figure 30: Changes to Integration Time FRAME_VALID N N+1 N+2 coarse_integration_time Pending Value coarse_integration_time Live Value Integration value used for read out frame old new value old new value old value new Changes to Gain Settings Usually, when the gain settings are changed, the gain is updated on the next frame start as is shown in Figure 31. When the integration time and the gain are changed at the same time, the gain update is held off by one frame so that the first frame output with the new integration time also has the new gain applied (Figure 32 on page 41). If the gain and integration time are both changed on successive frames, some gain values will be overwritten without ever being applied, while each integration time will be used for one single frame. Figure 31: Changes to Gain FRAME_VALID global_gain Pending Value global_gain Live Value n n+1 n+2 old new value old new value PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Registers Figure 32: Changes to Gain and Integration Time FRAME_VALID coarse_integration_time Pending Value coarse_integration_time Live Value Integration value used for read out frame global_gain Pending Value global_gain Live Value old old N N+1 N+2 new value old new value old value new value new old value new Embedded Data The current values of implemented registers in the address range 0x0000-0x0FFF can be generated as part of the pixel data. This embedded data is enabled by default. The current value of a register is the value that was used for the image data in that frame. In general, this is the live value of the register. The exceptions are: * The integration time is delayed by one further frame, so that the value corresponds to the integration time used for the image data in the frame. See "Changes to Integration Time" on page 40. * The PLL timing registers are not double-buffered, since the result of changing them in streaming mode is UNDEFINED. Therefore, the pending and live values for these registers are equivalent. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__2.fm - Rev. C 10/06 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Register List and Default Value Table 15: SMIA Configuration 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R0(R0x0000) R2(R0x0002) R3(R0x0003) R4(R0x0004) R5(R0x0005) R6(R0x0006) R8(R0x0008) R64(R0x0040) R65(R0x0041) R66(R0x0042) R68(R0x0044) R70(R0x0046) R72(R0x0048) R74(R0x004A) R76(R0x004C) R78(R0x004E) R80(R0x0050) R82(R0x0052) R84(R0x0054) R86(R0x0056) R88(R0x0058) R90(R0x005A) R92(R0x005C) R94(R0x005E) R128(R0x0080) R132(R0x0084) R134(R0x0086) R136(R0x0088) R138(R0x008A) R140(R0x008C) R142(R0x008E) R144(R0x0090) R146(R0x0092) R192(R0x00C0) R193(R0x00C1) R194(R0x00C2) R196(R0x00C4) Register Description model_id revision_number manufacturer_id smia_version frame_count pixel_order data_pedestal frame_format_model_type frame_format_model_subtype frame_format_descriptor_0 frame_format_descriptor_1 frame_format_descriptor_2 frame_format_descriptor_3 frame_format_descriptor_4 frame_format_descriptor_5 frame_format_descriptor_6 frame_format_descriptor_7 frame_format_descriptor_8 frame_format_descriptor_9 frame_format_descriptor_10 frame_format_descriptor_11 frame_format_descriptor_12 frame_format_descriptor_13 frame_format_descriptor_14 analogue_gain_capability analogue_gain_code_min analogue_gain_code_max analogue_gain_code_step analogue_gain_type analogue_gain_m0 analogue_gain_c0 analogue_gain_m1 analogue_gain_c1 data_format_model_type data_format_model_subtype data_format_descriptor_0 data_format_descriptor_1 Data Format (Binary) dddd dddd dddd dddd dddd dddd ???? ???? ???? ???? ???? ???? 0000 00?? 0000 dddd dddd dddd ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? Default Value Dec (Hex) 11008 (0x2B00) 0 (0x0000) 6 (0x0006) 10 (0x000A) 255 (0x00FF) 0 (0x0000) 168 (0x00A8) 1 (0x0001) 18 (0x0012) 23744 (0x5CC0) 4098 (0x1002) 22928 (0x5990) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 1 (0x0001) 8 (0x0008) 127 (0x007F) 1 (0x0001) 0 (0x0000) 1 (0x0001) 0 (0x0000) 0 (0x0000) 8 (0x0008) 1 (0x0001) 5 (0x0005) 2570 (0x0A0A) 2056 (0x0808) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 15: SMIA Configuration (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R198(R0x00C6) R200(R0x00C8) R202(R0x00CA) R204(R0x00CC) R206(R0x00CE) R256(R0x0100) R257(R0x0101) R259(R0x0103) R260(R0x0104) R261(R0x0105) R272(R0x0110) R273(R0x0111) R274(R0x0112) R288(R0x0120) R512(R0x0200) R514(R0x0202) R516(R0x0204) R518(R0x0206) R520(R0x0208) R522(R0x020A) R524(R0x020C) R526(R0x020E) R528(R0x0210) R530(R0x0212) R532(R0x0214) R768(R0x0300) R770(R0x0302) R772(R0x0304) R774(R0x0306) R776(R0x0308) R778(R0x030A) R832(R0x0340) R834(R0x0342) R836(R0x0344) R838(R0x0346) R840(R0x0348) R842(R0x034A) R844(R0x034C) R846(R0x034E) Register Description data_format_descriptor_2 data_format_descriptor_3 data_format_descriptor_4 data_format_descriptor_5 data_format_descriptor_6 mode_select image_orientation software_reset grouped_parameter_hold mask_corrupted_frames Reserved Reserved ccp_data_format gain_mode fine_integration_time coarse_integration_time analogue_gain_code_global analogue_gain_code_greenR analogue_gain_code_red analogue_gain_code_blue analogue_gain_code_greenB digital_gain_greenR digital_gain_red digital_gain_blue digital_gain_greenB vt_pix_clk_div vt_sys_clk_div pre_pll_clk_div pll_multiplier op_pix_clk_div op_sys_clk_div frame_length_lines line_length_pck x_addr_start y_addr_start x_addr_end y_addr_end x_output_size y_output_size Data Format (Binary) ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 0000 000d 0000 00dd 0000 000d 0000 000d 0000 000d 0000 0ddd 0000 000d 0000 ddd0 0000 ddd0 0000 000d dddd dddd dddd ddd0 dddd dddd dddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0ddd 0000 0000 0000 0ddd 0000 0000 0000 0ddd 0000 0000 0000 0ddd 0000 0000 0000 0000 0000 dddd 0000 0000 000d dddd 0000 0000 00dd dddd 0000 0000 dddd dddd 0000 0000 000d dddd 0000 0000 000d dddd dddd dddd dddd dddd dddd dddd dddd ddd0 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd ddd0 0000 dddd dddd ddd0 Default Value Dec (Hex) 2568 (0x0A08) 3084 (0x0C0C) 3080 (0x0C08) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 3084 (0x0C0C) 0 (0x0000) 1386 (0x056A) 16 (0x0010) 13 (0x000D) 13 (0x000D) 13 (0x000D) 13 (0x000D) 13 (0x000D) 256 (0x0100) 256 (0x0100) 256 (0x0100) 256 (0x0100) 4 (0x0004) 1 (0x0001) 2 (0x0002) 64 (0x0040) 8 (0x0008) 1 (0x0001) 2560 (0x0A00) 6558 (0x199E) 0 (0x0000) 8 (0x0008) 3263 (0x0CBF) 2455 (0x0997) 3264 (0x0CC0) 2448 (0x0990) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 15: SMIA Configuration (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R896(R0x0380) R898(R0x0382) R900(R0x0384) R902(R0x0386) R1024(R0x0400) R1026(R0x0402) R1028(R0x0404) R1030(R0x0406) R1280(R0x0500) R1536(R0x0600) R1538(R0x0602) R1540(R0x0604) R1542(R0x0606) R1544(R0x0608) R1546(R0x060A) R1548(R0x060C) R1550(R0x060E) R1552(R0x0610) Register Description x_even_inc x_odd_inc y_even_inc y_odd_inc scaling_mode spatial_sampling scale_m scale_n compression_mode test_pattern_mode test_data_red test_data_greenR test_data_blue test_data_greenB horizontal_cursor_width horizontal_cursor_position vertical_cursor_width vertical_cursor_position Data Format (Binary) 0000 0000 0000 000? 0000 0000 0000 0ddd 0000 0000 0000 000? 0000 0000 0000 0ddd 0000 0000 0000 00dd 0000 0000 0000 000d 0000 0000 dddd dddd 0000 0000 ???? ???? 0000 0000 0000 000? 0000 000d dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd Default Value Dec (Hex) 1 (0x0001) 1 (0x0001) 1 (0x0001) 1 (0x0001) 0 (0x0000) 0 (0x0000) 16 (0x0010) 16 (0x0010) 1 (0x0001) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) Table 16: 1: SMIA Parameter Limits 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Default Value Dec (Hex) 1 (0x0001) 0 (0x0000) 1 (0x0001) 1386 (0x056A) 938 (0x03AA) 1 (0x0001) 256 (0x0100) 1792 (0x0700) 256 (0x0100) 16576 (0x40C0) 0 (0x0000) 16960 (0x4240) 0 (0x0000) 1 (0x0001) 64 (0x0040) Register # Dec (Hex) R4096(R0x1000) R4100(R0x1004) R4102(R0x1006) R4104(R0x1008) R4106(R0x100A) R4224(R0x1080) R4228(R0x1084) R4230(R0x1086) R4232(R0x1088) R4352(R0x1100) R4354(R0x1102) R4356(R0x1104) R4358(R0x1106) R4360(R0x1108) R4362(R0x110A) Register Description integration_time_capability coarse_integration_time_min coarse_integration_time_max_margin fine_integration_time_min fine_integration_time_max_margin digital_gain_capability digital_gain_min digital_gain_max digital_gain_step_size min_ext_clk_freq_mhz_1 min_ext_clk_freq_mhz_2 max_ext_clk_freq_mhz_1 max_ext_clk_freq_mhz_2 min_pre_pll_clk_div max_pre_pll_clk_div Data Format (Binary) ???? ???? ???? ???? dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 16: 1: SMIA Parameter Limits (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R4364(R0x110C) R4366(R0x110E) R4368(R0x1110) R4370(R0x1112) R4372(R0x1114) R4374(R0x1116) R4376(R0x1118) R4378(R0x111A) R4380(R0x111C) R4382(R0x111E) R4384(R0x1120) R4386(R0x1122) R4388(R0x1124) R4390(R0x1126) R4392(R0x1128) R4394(R0x112A) R4396(R0x112C) R4398(R0x112E) R4400(R0x1130) R4402(R0x1132) R4404(R0x1134) R4406(R0x1136) R4416(R0x1140) R4418(R0x1142) R4420(R0x1144) R4422(R0x1146) R4424(R0x1148) R4426(R0x114A) R4448(R0x1160) R4450(R0x1162) R4452(R0x1164) R4454(R0x1166) R4456(R0x1168) R4458(R0x116A) R4460(R0x116C) R4462(R0x116E) R4464(R0x1170) R4466(R0x1172) R4468(R0x1174) Register Description min_pll_ip_freq_mhz_1 min_pll_ip_freq_mhz_2 max_pll_ip_freq_mhz_1 max_pll_ip_freq_mhz_2 min_pll_multiplier max_pll_multiplier min_pll_op_freq_mhz_1 min_pll_op_freq_mhz_2 max_pll_op_freq_mhz_1 max_pll_op_freq_mhz_2 min_vt_sys_clk_div max_vt_sys_clk_div min_vt_sys_clk_freq_mhz_1 min_vt_sys_clk_freq_mhz_2 max_vt_sys_clk_freq_mhz_1 max_vt_sys_clk_freq_mhz_2 min_vt_pix_clk_freq_mhz_1 min_vt_pix_clk_freq_mhz_2 max_vt_pix_clk_freq_mhz_1 max_vt_pix_clk_freq_mhz_2 min_vt_pix_clk_div max_vt_pix_clk_div min_frame_length_lines max_frame_length_lines min_line_length_pck max_line_length_pck min_line_blanking_pck min_frame_blanking_lines min_op_sys_clk_div max_op_sys_clk_div min_op_sys_clk_freq_mhz_1 min_op_sys_clk_freq_mhz_2 max_op_sys_clk_freq_mhz_1 max_op_sys_clk_freq_mhz_2 min_op_pix_clk_div max_op_pix_clk_div min_op_pix_clk_freq_mhz_1 min_op_pix_clk_freq_mhz_2 max_op_pix_clk_freq_mhz_1 Data Format (Binary) ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? Default Value Dec (Hex) 16384 (0x4000) 0 (0x0000) 16832 (0x41C0) 0 (0x0000) 32 (0x0020) 256 (0x0100) 17344 (0x43C0) 0 (0x0000) 17472 (0x4440) 0 (0x0000) 1 (0x0001) 1 (0x0001) 17344 (0x43C0) 0 (0x0000) 17472 (0x4440) 0 (0x0000) 17088 (0x42C0) 0 (0x0000) 17216 (0x4340) 0 (0x0000) 4 (0x0004) 4 (0x0004) 87 (0x0057) 65535 (0xFFFF) 2324 (0x0914) 65534 (0xFFFE) 1708 (0x06AC) 85 (0x0055) 1 (0x0001) 1 (0x0001) 17344 (0x43C0) 0 (0x0000) 17472 (0x4440) 0 (0x0000) 8 (0x0008) 8 (0x0008) 16960 (0x4240) 0 (0x0000) 17088 (0x42C0) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 16: 1: SMIA Parameter Limits (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R4470(R0x1176) R4480(R0x1180) R4482(R0x1182) R4484(R0x1184) R4486(R0x1186) R4544(R0x11C0) R4546(R0x11C2) R4548(R0x11C4) R4550(R0x11C6) R4608(R0x1200) R4612(R0x1204) R4614(R0x1206) R4616(R0x1208) R4618(R0x120A) R4864(R0x1300) R5120(R0x1400) R5122(R0x1402) R5124(R0x1404) R5126(R0x1406) R5128(R0x1408) R5130(R0x140A) R5132(R0x140C) R5134(R0x140E) R5136(R0x1410) Register Description max_op_pix_clk_freq_mhz_2 x_addr_min y_addr_min x_addr_max y_addr_max min_even_inc max_even_inc min_odd_inc max_odd_inc scaling_capability scaler_m_min scaler_m_max scaler_n_min scaler_n_max compression_capability matrix_element_RedInRed matrix_element_GreenInRed matrix_element_BlueInRed matrix_element_RedInGreen matrix_element_GreenInGreen matrix_element_BlueInGreen matrix_element_RedInBlue matrix_element_GreenInBlue matrix_element_BlueInBlue Data Format (Binary) ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd Default Value Dec (Hex) 0 (0x0000) 0 (0x0000) 0 (0x0000) 3279 (0x0CCF) 2463 (0x099F) 1 (0x0001) 1 (0x0001) 1 (0x0001) 3 (0x0003) 2 (0x0002) 16 (0x0010) 128 (0x0080) 16 (0x0010) 16 (0x0010) 1 (0x0001) 578 (0x0242) 65280 (0xFF00) 65470 (0xFFBE) 65460 (0xFFB4) 512 (0x0200) 65357 (0xFF4D) 65521 (0xFFF1) 65332 (0xFF34) 476 (0x01DC) Table 17: 3: Manufacturer Specific 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Default Value Dec (Hex) 11008 (0x2B00) 8 (0x0008) 0 (0x0000) 2455 (0x0997) 3263 (0x0CBF) 2560 (0x0A00) 6558 (0x199E) 256 (0x0100) 16 (0x0010) Register # Dec (Hex) R12288(R0x3000) R12290(R0x3002) R12292(R0x3004) R12294(R0x3006) R12296(R0x3008) R12298(R0x300A) R12300(R0x300C) R12304(R0x3010) R12306(R0x3012) Register Description model_id_ y_addr_start_ x_addr_start_ y_addr_end_ x_addr_end_ frame_length_lines_ line_length_pck_ fine_correction coarse_integration_time_ Data Format (Binary) dddd dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd ddd0 0ddd dddd dddd dddd dddd dddd dddd dddd PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R12308(R0x3014) R12310(R0x3016) R12312(R0x3018) R12314(R0x301A) R12316(R0x301C) R12317(R0x301D) R12318(R0x301E) R12321(R0x3021) R12322(R0x3022) R12323(R0x3023) R12324(R0x3024) R12326(R0x3026) R12328(R0x3028) R12330(R0x302A) R12332(R0x302C) R12334(R0x302E) R12336(R0x3030) R12338(R0x3032) R12340(R0x3034) R12342(R0x3036) R12344(R0x3038) R12346(R0x303A) R12347(R0x303B) R12348(R0x303C) R12352(R0x3040) R12356(R0x3044) R12358(R0x3046) R12360(R0x3048) R12374(R0x3056) R12376(R0x3058) R12378(R0x305A) R12380(R0x305C) R12382(R0x305E) R12384(R0x3060) R12386(R0x3062) R12388(R0x3064) R12390(R0x3066) R12392(R0x3068) R12394(R0x306A) Register Description fine_integration_time_ row_speed extra_delay reset_register mode_select_ image_orientation_ data_pedestal_ software_reset_ grouped_parameter_hold_ mask_corrupted_frames_ pixel_order_ gpi_status analogue_gain_code_global_ analogue_gain_code_greenR_ analogue_gain_code_red_ analogue_gain_code_blue_ analogue_gain_code_greenB_ digital_gain_greenR_ digital_gain_red_ digital_gain_blue_ digital_gain_greenB_ smia_version_ frame_count_ frame_status read_mode Reserved flash flash_count green1_gain blue_gain red_gain green2_gain global_gain Reserved Reserved Reserved Reserved Reserved datapath_status Data Format (Binary) dddd dddd dddd ddd0 0000 0ddd 0ddd 0ddd dddd dddd dddd ddd0 d00d 0ddd dd0d dddd 0000 000d 0000 00dd 0000 dddd dddd dddd 0000 000d 0000 000d 0000 000d 0000 00?? dddd dddd dddd ???? 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0000 0ddd dddd 0000 0ddd 0000 0000 0000 0ddd 0000 0000 0000 0ddd 0000 0000 0000 0ddd 0000 0000 ???? ???? ???? ???? 0000 0000 0000 00?? dd0d ddd0 dddd dddd - ??dd dddd 0000 0000 0000 00dd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd - - - - - 0000 0000 000d dddd Default Value Dec (Hex) 1386 (0x056A) 273 (0x0111) 0 (0x0000) 88 (0x0058) 0 (0x0000) 0 (0x0000) 168 (0x00A8) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 65535 (0xFFFF) 13 (0x000D) 13 (0x000D) 13 (0x000D) 13 (0x000D) 13 (0x000D) 256 (0x0100) 256 (0x0100) 256 (0x0100) 256 (0x0100) 10 (0x000A) 255 (0x00FF) 0 (0x0000) 36 (0x0024) 34112 (0x8540) 1536 (0x0600) 8 (0x0008) 564 (0x0234) 564 (0x0234) 564 (0x0234) 564 (0x0234) 564 (0x0234) 5376 (0x1500) 0 (0x0000) 261 (0x0105) 0 (0x0000) 2730 (0x0AAA) 0 (0x0000) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R12396(R0x306C) R12398(R0x306E) R12400(R0x3070) R12402(R0x3072) R12404(R0x3074) R12406(R0x3076) R12408(R0x3078) R12416(R0x3080) R12418(R0x3082) R12420(R0x3084) R12422(R0x3086) R12424(R0x3088) R12426(R0x308A) R12428(R0x308C) R12430(R0x308E) R12432(R0x3090) R12434(R0x3092) R12436(R0x3094) R12438(R0x3096) R12440(R0x3098) R12442(R0x309A) R12444(R0x309C) R12446(R0x309E) R12448(R0x30A0) R12450(R0x30A2) R12452(R0x30A4) R12454(R0x30A6) R12490(R0x30CA) R12492(R0x30CC) R12494(R0x30CE) R12496(R0x30D0) R12498(R0x30D2) R12500(R0x30D4) R12502(R0x30D6) R12504(R0x30D8) R12506(R0x30DA) R12510(R0x30DE) R12512(R0x30E0) R12514(R0x30E2) Register Description Reserved datapath_select test_pattern_mode_ test_data_red_ test_data_greenR_ test_data_blue_ test_data_greenB_ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved x_even_inc_ x_odd_inc_ y_even_inc_ y_odd_inc_ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Data Format (Binary) - dddd dd00 d00d 0000 0000 000d 0000 0ddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd - - - - - - - - - - - - - - - - 0000 0000 0000 000? 0000 0000 0000 0ddd 0000 0000 0000 000? 0000 0000 0000 0ddd - - - - - - - - - - - - Default Value Dec (Hex) 32768 (0x8000) 36992 (0x9080) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 164 (0x00A4) 4369 (0x1111) 9252 (0x2424) 9321 (0x2469) 26096 (0x65F0) 25700 (0x6464) 14483 (0x3893) 5654 (0x1616) 22102 (0x5656) 2660 (0x0A64) 25700 (0x6464) 25700 (0x6464) 27684 (0x6C24) 44288 (0xAD00) 6400 (0x1900) 25856 (0x6500) 1 (0x0001) 1 (0x0001) 1 (0x0001) 1 (0x0001) 4 (0x0004) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 32896 (0x8080) 2048 (0x0800) 0 (0x0000) 0 (0x0000) 17 (0x0011) 46594 (0xB602) 37475 (0x9263) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R12516(R0x30E4) R12518(R0x30E6) R12520(R0x30E8) R12522(R0x30EA) R12524(R0x30EC) R12526(R0x30EE) R12528(R0x30F0) R12530(R0x30F2) R12532(R0x30F4) R12534(R0x30F6) R12536(R0x30F8) R12538(R0x30FA) R12540(R0x30FC) R12542(R0x30FE) R12544(R0x3100) R12546(R0x3102) R12548(R0x3104) R12550(R0x3106) R12552(R0x3108) R12554(R0x310A) R12556(R0x310C) R12558(R0x310E) R12560(R0x3110) R12562(R0x3112) R12564(R0x3114) R12566(R0x3116) R12568(R0x3118) R12570(R0x311A) R12572(R0x311C) R12574(R0x311E) R12576(R0x3120) R12578(R0x3122) R12580(R0x3124) R12582(R0x3126) R12584(R0x3128) R12586(R0x312A) R12588(R0x312C) R12590(R0x312E) R12608(R0x3140) Register Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Data Format (Binary) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Default Value Dec (Hex) 46226 (0xB492) 46083 (0xB403) 255 (0x00FF) 13059 (0x3303) 25395 (0x6333) 255 (0x00FF) 255 (0x00FF) 46083 (0xB403) 255 (0x00FF) 2048 (0x0800) 2048 (0x0800) 2048 (0x0800) 2048 (0x0800) 28761 (0x7059) 28761 (0x7059) 37233 (0x9171) 45203 (0xB093) 12809 (0x3209) 22579 (0x5833) 46082 (0xB402) 46082 (0xB402) 46089 (0xB409) 46337 (0xB501) 46081 (0xB401) 1795 (0x0703) 46338 (0xB502) 0 (0x0000) 28772 (0x7064) 0 (0x0000) 2048 (0x0800) 0 (0x0000) 2048 (0x0800) 255 (0x00FF) 46594 (0xB602) 46088 (0xB408) 255 (0x00FF) 176 (0x00B0) 13494 (0x34B6) 13313 (0x3401) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R12610(R0x3142) R12612(R0x3144) R12614(R0x3146) R12616(R0x3148) R12618(R0x314A) R12620(R0x314C) R12622(R0x314E) R12624(R0x3150) R12628(R0x3154) R12630(R0x3156) R12632(R0x3158) R12634(R0x315A) R12640(R0x3160) R12642(R0x3162) R12644(R0x3164) R12646(R0x3166) R12652(R0x316C) R12654(R0x316E) R12656(R0x3170) R12660(R0x3174) R12662(R0x3176) R12664(R0x3178) R12672(R0x3180) R12674(R0x3182) R12676(R0x3184) R12678(R0x3186) R12680(R0x3188) R12682(R0x318A) R12684(R0x318C) R12686(R0x318E) R12688(R0x3190) R12690(R0x3192) R12692(R0x3194) R12694(R0x3196) R12696(R0x3198) R12776(R0x31E8) R12778(R0x31EA) R12780(R0x31EC) R12782(R0x31EE) Register Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved global_seq_trigger global_rst_end global_shutter_start global_read_start Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved horizontal_cursor_position_ vertical_cursor_position_ horizontal_cursor_width_ vertical_cursor_width_ Data Format (Binary) - - - - - - - - - - - - 0000 00?? 0000 0ddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd - - - - - - - - - - - - - - - - - - - 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd Default Value Dec (Hex) 13058 (0x3302) 12803 (0x3203) 11524 (0x2D04) 11269 (0x2C05) 11524 (0x2D04) 0 (0x0000) 13058 (0x3302) 0 (0x0000) 5249 (0x1481) 7297 (0x1C81) 0 (0x0000) 0 (0x0000) 0 (0x0000) 80 (0x0050) 120 (0x0078) 160 (0x00A0) 17424 (0x4410) 1024 (0x0400) 11686 (0x2DA6) 4626 (0x1212) 4626 (0x1212) 4626 (0x1212) 36863 (0x8FFF) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R12788(R0x31F4) R12790(R0x31F6) R12792(R0x31F8) R12794(R0x31FA) R12796(R0x31FC) R12798(R0x31FE) R13824(R0x3600) R13826(R0x3602) R13828(R0x3604) R13830(R0x3606) R13832(R0x3608) R13834(R0x360A) R13836(R0x360C) R13838(R0x360E) R13840(R0x3610) R13842(R0x3612) R13844(R0x3614) R13846(R0x3616) R13848(R0x3618) R13850(R0x361A) R13852(R0x361C) R13854(R0x361E) R13856(R0x3620) R13858(R0x3622) R13860(R0x3624) R13862(R0x3626) R13888(R0x3640) R13890(R0x3642) R13892(R0x3644) R13894(R0x3646) R13896(R0x3648) R13898(R0x364A) R13900(R0x364C) R13902(R0x364E) R13904(R0x3650) R13906(R0x3652) R13908(R0x3654) R13910(R0x3656) R13912(R0x3658) 2 Register Description Reserved Reserved Reserved Reserved 1 C Addresses Reserved P_GR_P0Q0 P_GR_P0Q1 P_GR_P0Q2 P_GR_P0Q3 P_GR_P0Q4 P_RD_P0Q0 P_RD_P0Q1 P_RD_P0Q2 P_RD_P0Q3 P_RD_P0Q4 P_BL_P0Q0 P_BL_P0Q1 P_BL_P0Q2 P_BL_P0Q3 P_BL_P0Q4 P_GB_P0Q0 P_GB_P0Q1 P_GB_P0Q2 P_GB_P0Q3 P_GB_P0Q4 P_GR_P1Q0 P_GR_P1Q1 P_GR_P1Q2 P_GR_P1Q3 P_GR_P1Q4 P_RD_P1Q0 P_RD_P1Q1 P_RD_P1Q2 P_RD_P1Q3 P_RD_P1Q4 P_BL_P1Q0 P_BL_P1Q1 P_BL_P1Q2 Data Format (Binary) - - - - - - dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd Default Value Dec (Hex) 291 (0x0123) 17767 (0x4567) 35243 (0x89AB) 52719 (0xCDEF) 12320 (0x3020) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R13914(R0x365A) R13916(R0x365C) R13918(R0x365E) R13920(R0x3660) R13922(R0x3662) R13924(R0x3664) R13926(R0x3666) R13952(R0x3680) R13954(R0x3682) R13956(R0x3684) R13958(R0x3686) R13960(R0x3688) R13962(R0x368A) R13964(R0x368C) R13966(R0x368E) R13968(R0x3690) R13970(R0x3692) R13972(R0x3694) R13974(R0x3696) R13976(R0x3698) R13978(R0x369A) R13980(R0x369C) R13982(R0x369E) R13984(R0x36A0) R13986(R0x36A2) R13988(R0x36A4) R13990(R0x36A6) R14016(R0x36C0) R14018(R0x36C2) R14020(R0x36C4) R14022(R0x36C6) R14024(R0x36C8) R14026(R0x36CA) R14028(R0x36CC) R14030(R0x36CE) R14032(R0x36D0) R14034(R0x36D2) R14036(R0x36D4) R14038(R0x36D6) Register Description P_BL_P1Q3 P_BL_P1Q4 P_GB_P1Q0 P_GB_P1Q1 P_GB_P1Q2 P_GB_P1Q3 P_GB_P1Q4 P_GR_P2Q0 P_GR_P2Q1 P_GR_P2Q2 P_GR_P2Q3 P_GR_P2Q4 P_RD_P2Q0 P_RD_P2Q1 P_RD_P2Q2 P_RD_P2Q3 P_RD_P2Q4 P_BL_P2Q0 P_BL_P2Q1 P_BL_P2Q2 P_BL_P2Q3 P_BL_P2Q4 P_GB_P2Q0 P_GB_P2Q1 P_GB_P2Q2 P_GB_P2Q3 P_GB_P2Q4 P_GR_P3Q0 P_GR_P3Q1 P_GR_P3Q2 P_GR_P3Q3 P_GR_P3Q4 P_RD_P3Q0 P_RD_P3Q1 P_RD_P3Q2 P_RD_P3Q3 P_RD_P3Q4 P_BL_P3Q0 P_BL_P3Q1 Data Format (Binary) dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd Default Value Dec (Hex) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R14040(R0x36D8) R14042(R0x36DA) R14044(R0x36DC) R14046(R0x36DE) R14048(R0x36E0) R14050(R0x36E2) R14052(R0x36E4) R14054(R0x36E6) R14080(R0x3700) R14082(R0x3702) R14084(R0x3704) R14086(R0x3706) R14088(R0x3708) R14090(R0x370A) R14092(R0x370C) R14094(R0x370E) R14096(R0x3710) R14098(R0x3712) R14100(R0x3714) R14102(R0x3716) R14104(R0x3718) R14106(R0x371A) R14108(R0x371C) R14110(R0x371E) R14112(R0x3720) R14114(R0x3722) R14116(R0x3724) R14118(R0x3726) R14144(R0x3740) R14146(R0x3742) R14148(R0x3744) R14150(R0x3746) R14152(R0x3748) R14160(R0x3750) R14162(R0x3752) R14164(R0x3754) R14166(R0x3756) R14168(R0x3758) R14208(R0x3780) Register Description P_BL_P3Q2 P_BL_P3Q3 P_BL_P3Q4 P_GB_P3Q0 P_GB_P3Q1 P_GB_P3Q2 P_GB_P3Q3 P_GB_P3Q4 P_GR_P4Q0 P_GR_P4Q1 P_GR_P4Q2 P_GR_P4Q3 P_GR_P4Q4 P_RD_P4Q0 P_RD_P4Q1 P_RD_P4Q2 P_RD_P4Q3 P_RD_P4Q4 P_BL_P4Q0 P_BL_P4Q1 P_BL_P4Q2 P_BL_P4Q3 P_BL_P4Q4 P_GB_P4Q0 P_GB_P4Q1 P_GB_P4Q2 P_GB_P4Q3 P_GB_P4Q4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SC_ENABLE Data Format (Binary) dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd - - - - - - - - - - d000 0000 0000 0000 Default Value Dec (Hex) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register List and Default Value Table 17: 3: Manufacturer Specific (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable;? = read-only, dynamic Register # Dec (Hex) R14210(R0x3782) R14212(R0x3784) R15872(R0x3E00) R16128(R0x3F00) Register Description ORIGIN_C ORIGIN_R Reserved Reserved Data Format (Binary) 0000 dddd dddd dddd 0000 dddd dddd dddd - - Default Value Dec (Hex) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__3reg.fm - Rev. C 10/06 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Register Description Table 18: Reg. # R0 R0x0000 R2 R0x0002 R3 R0x0003 R4 R0x0004 R5 R0x0005 R6 R0x0006 R8 R0x0008 R64 R0x0040 R65 R0x0041 R66 R0x0042 R68 R0x0044 0: SMIA Configuration Bits 15:0 Default 0x2B00 model_id (RW) Name Frame Sync'd N Bad Frame N This register is an alias of R0x3000-1. Read-only. Can be made read/write by clearing R0x301A-B[3]. 7:0 0x0000 N N revision_number (RW) Micron Imaging assigned revision number. Read-only. Can be made read/write by clearing R0x301A-B[3]. 7:0 0x0006 N N manufacturer_id (RO) Manufacturer ID assigned to Micron Imaging. Read-only. Can be made read/write by clearing R0x301AB[3]. 7:0 0x000A N N smia_version (RO) This register is an alias of R0x303A. Read-only. 7:0 0x00FF frame_count (RO) This register is an alias of R0x303B. Read-only. 7:0 0x0000 pixel_order (RO) This register is an alias of R0x3024. Read-only. 15:0 0x00A8 data_pedestal (RW) Y N N N N Y This register is an alias of R0x301E-F. Read-only. Can be made read/write by clearing R0x301A-B[3]. 7:0 0x0001 N N frame_format_model_type (RO) Type 1. 2-byte Generic Frame Format Description. Read-only. 7:0 0x0012 frame_format_model_subtype (RO) N N N Number of descriptors: 1 X (column) descriptor and two Y (row) descriptors. Read-only. 15:0 0x5CC0 Y frame_format_descriptor_0 (RO) X descriptor: Bits[11:0] of this register reflect the current value of x_output_size[11:0]. Upper 4 bits is the pixel code; 5=Visible Pixel Data. Read-only, dynamic. 15:0 0x1002 Y N frame_format_descriptor_1 (RO) Y descriptor: In normal operation, returns 0x1002 to indicate that 2 rows of embedded data are present in the output image. If embedded data is disabled (by selecting the PN9 test pattern using R0x3070-1) this register will return 0x1000. Read-only. 15:0 0x5990 Y N frame_format_descriptor_2 (RO) Y descriptor: Bits[11:0] of this register reflect the current value of y_output_size[11:0]. Upper 4 bits is the pixel code; 5=Visible Pixel Data. Read-only, dynamic. 15:0 0x0000 N N frame_format_descriptor_3 (RO) Read-only. 15:0 Read-only. 15:0 Read-only. 15:0 Read-only. 15:0 Read-only. 15:0 Read-only. 0x0000 0x0000 0x0000 0x0000 0x0000 frame_format_descriptor_4 (RO) frame_format_descriptor_5 (RO) frame_format_descriptor_6 (RO) frame_format_descriptor_7 (RO) frame_format_descriptor_8 (RO) N N N N N N N N N N R70 R0x0046 R72 R0x0048 R74 R0x004A R76 R0x004C R78 R0x004E R80 R0x0050 R82 R0x0052 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 18: Reg. # R84 R0x0054 R86 R0x0056 R88 R0x0058 R90 R0x005A R92 R0x005C R94 R0x005E R128 R0x0080 R132 R0x0084 R134 R0x0086 R136 R0x0088 R138 R0x008A R140 R0x008C R142 R0x008E R144 R0x0090 R146 R0x0092 R192 R0x00C0 R193 R0x00C1 R194 R0x00C2 R196 R0x00C4 0: SMIA Configuration (continued) Bits 15:0 Read-only. 15:0 Read-only. 15:0 Read-only. 15:0 Read-only. 15:0 Read-only. 15:0 Read-only. 15:0 Default 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 Name frame_format_descriptor_9 (RO) frame_format_descriptor_10 (RO) frame_format_descriptor_11 (RO) frame_format_descriptor_12 (RO) frame_format_descriptor_13 (RO) frame_format_descriptor_14 (RO) analogue_gain_capability (RO) Frame Sync'd N N N N N N N Bad Frame N N N N N N N Indicates the provision of separate (per-color) analog gain control. The sensor supports both global and separate (per-color) analog gain control. Read-only. 15:0 0x0008 N N analogue_gain_code_min (RO) Minimum gain code. Read-only. 15:0 0x007F analogue_gain_code_max (RO) Maximum gain code. Read-only. 15:0 0x0001 analogue_gain_code_step (RO) Gain code step size. Read-only. 15:0 0x0000 analogue_gain_type (RO) N N N N N N N N N N N N N N N N N N N N Indicates support for analog gain coding type 0 (baseline SMIA). Read-only. 15:0 0x0001 analogue_gain_m0 (RO) Constants for the gain equation. Read-only. 15:0 0x0000 analogue_gain_c0 (RO) Constants for the gain equation. Read-only. 15:0 0x0000 analogue_gain_m1 (RO) Constants for the gain equation. Read-only. 15:0 0x0008 analogue_gain_c1 (RO) Constants for the gain equation. Read-only. 7:0 0x0001 data_format_model_type (RO) Indicates the use of 2-byte data format. Read-only. 7:0 0x0005 data_format_model_subtype (RO) Indicates the provision of 5 data format descriptors. Read-only. 15:0 0x0A0A data_format_descriptor_0 (RO) Indicates support for RAW10 data format in which the two LSB of each 12-bit pixel data value are discarded. Read-only. 15:0 0x0808 N N data_format_descriptor_1 (RO) Indicates support for RAW8 data format in which the four LSB of each 12-bit pixel data value are discarded. Read-only. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 18: Reg. # R198 R0x00C6 R200 R0x00C8 R202 R0x00CA R204 R0x00CC R206 R0x00CE R256 R0x0100 R257 R0x0101 0: SMIA Configuration (continued) Bits 15:0 Default 0x0A08 Name data_format_descriptor_2 (RO) Frame Sync'd N Bad Frame N Indicates support for RAW8 data format in which each truncated 10-bit pixel data value is compressed to an 8-bit value. Read-only. 15:0 0x0C0C N N data_format_descriptor_3 (RO) Indicates support for RAW12, uncompressed data format. Read-only. 15:0 0x0C08 data_format_descriptor_4 (RO) N N Indicates support for RAW8 data format in which each 12-bit pixel data value is compressed to an 8-bit value. Read-only. 15:0 0x0000 N N data_format_descriptor_5 (RO) Read-only. 15:0 Read-only. 7:0 0x0000 0x0000 data_format_descriptor_6 (RO) mode_select (RW) N Y N N This register field is an alias of R0x301A[2]. 7:0 0x0000 image_orientation (RW) 7:2 X Reserved 1 0x0000 Vertical Flip This register field is an alias of R0x3040-1[1]. Horizontal Mirror This register field is an alias of R0x3040-1[0]. software_reset (RW) Y YM 0 0x0000 Y YM R259 R0x0103 R260 R0x0104 R261 R0x0105 R272 R0x0110 R273 R0x0111 R274 R0x0112 7:0 0x0000 N N N Y Y Y Y N Y N N N This register field is an alias of R0x301A-B[0]. 7:0 0x0000 grouped_parameter_hold (RW) This register field is an alias of R0x301A-B[15]. 7:0 0x0000 mask_corrupted_frames (RW) This register field is an alias of R0x301A-B[9]. 7:0 0x0000 Reserved (RW) Not used. 7:0 Not used. 15:0 0x0000 0x0C0C Reserved (RW) ccp_data_format (RW) R288 R0x0120 R512 R0x0200 R514 R0x0202 [7:0] = The bit-width of the compressed pixel data [15:8] = The bit-width of the uncompressed pixel data The value in this register must match one of the valid data_format_descriptor registers (R0x00C2R0x00C7). 7:0 0x0000 N N gain_mode (RW) This read/write bit has no function. 15:0 0x056A fine_integration_time (RW) Y N N Integration time programmed in units of pck. This register is an alias of R0x3014-5. 15:0 0x0010 Y coarse_integration_time (RW) Integration time programmed in units of line_length_pck. This register is an alias of R0x3012-3. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 18: Reg. # R516 R0x0204 R518 R0x0206 R520 R0x0208 R522 R0x020A R524 R0x020C R526 R0x020E R528 R0x0210 R530 R0x0212 R532 R0x0214 R768 R0x0300 R770 R0x0302 R772 R0x0304 R774 R0x0306 R776 R0x0308 R778 R0x030A R832 R0x0340 R834 R0x0342 R836 R0x0344 R838 R0x0346 R840 R0x0348 R842 R0x034A 0: SMIA Configuration (continued) Bits 15:0 Default 0x000D Name analogue_gain_code_global (RW) Frame Sync'd Y Y Y Y Y Y Y Y Y N N Bad Frame N N N N N N N N N Y N Y Y Y This register is an alias of R0x3028-9. 15:0 0x000D analogue_gain_code_green1 (RW) This register is an alias of R0x302A-B. 15:0 0x000D analogue_gain_code_red (RW) This register is an alias of R0x302C-D. 15:0 0x000D analogue_gain_code_blue (RW) This register is an alias of R0x302E-F. 15:0 0x000D analogue_gain_code_green2 (RW) This register is an alias of R0x3030-1. 15:0 0x0100 digital_gain_green1 (RW) This register is an alias of R0x3032-3. 15:0 0x0100 digital_gain_red (RW) This register is an alias of R0x3034-5. 15:0 0x0100 digital_gain_blue (RW) This register is an alias of R0x3036-7. 15:0 0x0100 digital_gain_green2 (RW) This register is an alias of R0x3038-9. 15:0 0x0004 vt_pix_clk_div (RW) Not in use. Use pc_speed[2:0] to change vt_pix_clk_mhz instead. 15:0 0x0001 vt_sys_clk_div (RW) Clock divisor applied to PLL output clock to generate video timing system clock. Read-only. 15:0 0x0002 N pre_pll_clk_div (RW) Clock divisor applied to EXTCLK to generate PLL input clock. 15:0 0x0040 pll_multiplier (RW) Clock multiplier applied to PLL input clock. 15:0 0x0008 op_pix_clk_div (RW) N N Clock divisor applied to the output system clock to generate the output pixel clock. Legal values are 1, 2 and 4. 15:0 0x0001 N Y op_sys_clk_div (RW) Clock divisor applied to PLL output clock to generate output system clock. Read-only. 15:0 0x0A00 Y frame_length_lines (RW) This register is an alias of R0x300A-B. 15:0 0x199E line_length_pck (RW) This register is an alias of R0x300C-D. 15:0 0x0000 x_addr_start (RW) This register is an alias of R0x3004-5. 15:0 0x0008 y_addr_start (RW) This register is an alias of R0x3002-5. 15:0 0x0CBF x_addr_end (RW) This register is an alias of R0x3008-9. 15:0 0x0997 y_addr_end (RW) This register is an alias of R0x3006-7. Y Y Y Y Y YM YM N YM N YM PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 18: Reg. # R844 R0x034C R846 R0x034E 0: SMIA Configuration (continued) Bits 15:0 Default 0x0CC0 Name x_output_size (RW) Frame Sync'd Y Bad Frame N Set X output size of displayed image. Bit[0] is read-only 0. The default value of this register is set to be consistent with the default values of x_addr_end and x_addr_start. 15:0 0x0990 Y N y_output_size (RW) Set Y output size of the displayed image. Bit[0] is read-only 0. The default value of this registers set to be consistent with the default values of y_addr_end and y_addr_start. The output image will have two additional rows containing embedded data, in accordance with the frame format descriptors. 15:0 0x0001 N N x_even_inc (RO) Read-only. The fixed value of "1" constrains subsampling operation to use adjacent pixels of a pixel quad. 15:0 0x0001 Y YM x_odd_inc (RW) This register field is an alias of R0x3040-1[7:5]. 15:0 0x0001 y_even_inc (RO) N N R896 R0x0380 R898 R0x0382 R900 R0x0384 R902 R0x0386 R1024 R0x0400 Read-only. The fixed value of "1" constrains subsampling operation to use adjacent pixels of a pixel quad. 15:0 0x0001 Y YM y_odd_inc (RW) This register field is an alias of R0x3040-1[4:2]. 15:0 0x0000 scaling_mode (RW) 0 = Disable scaler 1 = Enable horizontal scaling 2 = Enable horizontal and vertical scaling 3 = Reserved 15:0 0x0000 spatial_sampling (RW) 0 = Bayer sampling 1 = Co-sited sampling 15:0 0x0010 Scale factor M. 15:0 0x0010 Y N R1026 R0x0402 R1028 R0x0404 R1030 R0x0406 R1280 R0x0500 Y N scale_m (RW) scale_n (RO) compression_mode (RO) Y N N N N Y Scale factor N. Read-only. 15:0 0x0001 R1536 R0x0600 R1538 R0x0602 R1540 R0x0604 R1542 R0x0606 R1544 R0x0608 0x0001 = 10-bit to 8-bit and 12-bit to 8-bit compression uses the DPCM/PCM Simple Predictor algorithm. Read-only. This register controls the algorithm that is to be used for compression. The sensor only supports a single algorithm and therefore this register is read-only. This register does not control whether data compression is enabled; that is controlled by the ccp_data_format register (R0x0012-3). 15:0 0x0000 N Y test_pattern_mode (RW) This register is an alias of R0x3070-1. 15:0 0x0000 test_data_red (RW) This register is an alias of R0x3072-3. 15:0 0x0000 test_data_green1 (RW) This register is an alias of R0x3074-5. 15:0 0x0000 test_data_blue (RW) This register is an alias of R0x3076-7. 15:0 0x0000 test_data_green2 (RW) This register is an alias of R0x3078-8. N N N N Y Y Y Y PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 18: Reg. # R1546 R0x060A R1548 R0x060C R1550 R0x060E R1552 R0x0610 0: SMIA Configuration (continued) Bits 15:0 Default 0x0000 Name horizontal_cursor_width (RW) Frame Sync'd N N N N Bad Frame N N N N This register is an alias of R0x31EC-D. 15:0 0x0000 horizontal_cursor_position (RW) This register is an alias of R0x31E8-9. 15:0 0x0000 vertical_cursor_width (RW) This register is an alias of R0x31EE-F. 15:0 0x0000 vertical_cursor_position (RW) This register is an alias of R0x31EA-B. Table 19: Reg. # R4096 R0x1000 R4100 R0x1004 R4102 R0x1006 1: SMIA Parameter Limits Bits 15:0 Default 0x0001 Name integration_time_capability (RO) Frame Sync'd N Bad Frame N Indicates the provision of coarse and fine integration time control. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0000 N N coarse_integration_time_min (RW) The minimum coarse integration time. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0001 N N coarse_integration_time_max_margin (RW) The maximum coarse integration time is (frame_length_lines - coarse_integration_time_max_margin). Read-only. Can be made read/write by clearing R0x301A-B[3]. In the sensor, this limit can be broken. The result will be a graceful degradation of frame rate, like premi3120 products. 15:0 0x056A N N fine_integration_time_min (RW) The minimum fine integration time. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x03AA N N fine_integration_time_max_margin (RW) The minimum fine integration time is (line_length_pck - fine_integration_time_max_margin). Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0001 N N digital_gain_capability (RO) Indicates the provision of separate (per-color) digital gain control. Read-only. 15:0 0x0100 digital_gain_min (RO) UFIX16. Minimum value of digital gain is 1.0. Read-only. 15:0 0x0700 digital_gain_max (RO) UFIX16. Maximum value of digital gain is 4.0. Read-only. 15:0 0x0100 digital_gain_step_size (RO) UFIX16. Step size for digital gain is 1.0. Read-only. 15:0 0x40C0 min_ext_clk_freq_mhz_1 (RO) FLP32. Minimum external clock frequency into PLL is 6 MHz. Read-only. 15:0 0x0000 min_ext_clk_freq_mhz_2 (RO) FLP32. Minimum external clock frequency into PLL is 6 MHz. Read-only. N N N N N N N N N N R4104 R0x1008 R4106 R0x100A R4224 R0x1080 R4228 R0x1084 R4230 R0x1086 R4232 R0x1088 R4352 R0x1100 R4354 R0x1102 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 19: Reg. # R4356 R0x1104 R4358 R0x1106 R4360 R0x1108 R4362 R0x110A R4364 R0x110C R4366 R0x110E R4368 R0x1110 R4370 R0x1112 R4372 R0x1114 R4374 R0x1116 R4376 R0x1118 R4378 R0x111A R4380 R0x111C R4382 R0x111E R4384 R0x1120 R4386 R0x1122 R4388 R0x1124 R4390 R0x1126 R4392 R0x1128 R4394 R0x112A R4396 R0x112C 1: SMIA Parameter Limits (continued) Bits 15:0 Default 0x4240 Name max_ext_clk_freq_mhz_1 (RO) Frame Sync'd N N N N N N N N N N N N N N N N N N N N N Bad Frame N N N N N N N N N N N N N N N N N N N N N FLP32. Maximum external clock frequency into PLL is 48 MHz. Read-only. 15:0 0x0000 max_ext_clk_freq_mhz_2 (RO) FLP32. Maximum external clock frequency into PLL is 48 MHz. Read-only. 15:0 0x0001 min_pre_pll_clk_div (RO) Minimum clock divisor applied to PLL input clock. Read-only. 15:0 0x0040 max_pre_pll_clk_div (RO) Maximum clock divisor applied to PLL input clock. Read-only. 15:0 0x4000 min_pll_ip_freq_mhz_1 (RO) FLP32. Minimum clock frequency into the PFD of the PLL is 2 MHz. Read-only. 15:0 0x0000 min_pll_ip_freq_mhz_2 (RO) FLP32. Minimum clock frequency into the PFD of the PLL is 2 MHz. Read-only. 15:0 0x41C0 max_pll_ip_freq_mhz_1 (RO) FLP32. Maximum clock frequency into the PFD of the PLL is 22.5 MHz. Read-only. 15:0 0x0000 max_pll_ip_freq_mhz_2 (RO) FLP32. Maximum clock frequency into the PFD of the PLL is 22.5 MHz. Read-only. 15:0 0x0020 min_pll_multiplier (RO) Minimum multiplier applied by PLL. Read-only. 15:0 0x0100 max_pll_multiplier (RO) Maximum multiplier applied by PLL. Read-only. 15:0 0x43C0 min_pll_op_freq_mhz_1 (RO) FLP32. Minimum output frequency supported by the PLL is 160 MHz. Read-only. 15:0 0x0000 min_pll_op_freq_mhz_2 (RO) FLP32. Minimum output frequency supported by the PLL is 160 MHz. Read-only. 15:0 0x4440 max_pll_op_freq_mhz_1 (RO) FLP32. Maximum output frequency supported by the PLL is 768 MHz. Read-only. 15:0 0x0000 max_pll_op_freq_mhz_2 (RO) FLP32. Maximum output frequency supported by the PLL is 768 MHz. Read-only. 15:0 0x0001 min_vt_sys_clk_div (RO) The video timing sys_clk has a fixed divisor. Read-only. 15:0 0x0001 max_vt_sys_clk_div (RO) The video timing sys_clk has a fixed divisor. Read-only. 15:0 0x43C0 min_vt_sys_clk_freq_mhz_1 (RO) FLP32. Minimum frequency for the video timing sys_clk is 40 MHz. 15:0 0x0000 min_vt_sys_clk_freq_mhz_2 (RO) FLP32. Minimum frequency for the video timing sys_clk is 40 MHz. 15:0 0x4440 max_vt_sys_clk_freq_mhz_1 (RO) Maximum frequency for the video timing sys_clk is 192 MHz. Read-only. 15:0 0x0000 max_vt_sys_clk_freq_mhz_2 (RO) Maximum frequency for the video timing sys_clk is 192 MHz. Read-only. 15:0 0x42C0 min_vt_pix_clk_freq_mhz_1 (RO) FLP32. Minimum frequency for video timing pix_clk is 10 MHz. Read-only. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 19: Reg. # R4398 R0x112E R4400 R0x1130 R4402 R0x1132 R4404 R0x1134 R4406 R0x1136 R4416 R0x1140 R4418 R0x1142 R4420 R0x1144 R4422 R0x1146 R4424 R0x1148 R4426 R0x114A R4448 R0x1160 R4450 R0x1162 R4452 R0x1164 R4454 R0x1166 R4456 R0x1168 R4458 R0x116A R4460 R0x116C R4462 R0x116E R4464 R0x1170 1: SMIA Parameter Limits (continued) Bits 15:0 Default 0x0000 Name min_vt_pix_clk_freq_mhz_2 (RO) Frame Sync'd N N N N N N Bad Frame N N N N N N N FLP32. Minimum frequency for video timing pix_clk is 10 MHz. Read-only. 15:0 0x4340 max_vt_pix_clk_freq_mhz_1 (RO) FLP32. Maximum frequency for video timing pix_clk is 192 MHz. Read-only. 15:0 0x0000 max_vt_pix_clk_freq_mhz_2 (RO) FLP32. Maximum frequency for video timing pix_clk is 192 MHz. Read-only. 15:0 0x0004 min_vt_pix_clk_div (RO) Minimum divisor for the video timing pix_clk. Read-only. 15:0 0x0004 max_vt_pix_clk_div (RO) Maximum divisor for the video timing pix_clk. Read-only. 15:0 0x0057 min_frame_length_lines (RW) Minimum frame length. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0xFFFF N max_frame_length_lines (RW) Maximum frame length. The maximum frame length is only constrained by the size of the read/write field in the frame_length_lines register (16-bits). Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0914 N N min_line_length_pck (RW) Minimum line length. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0xFFFE N max_line_length_pck (RW) N Maximum line length. The maximum line length is only constrained by the size of the read/write field in the line_length_pck register (16 bits). Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x06AC N N min_line_blanking_pck (RW) Minimum line blanking time. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0055 N min_frame_blanking_lines (RW) Minimum frame blanking time. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0001 N min_op_sys_clk_div (RO) Minimum divisor for the output sys_clk. Read-only. 15:0 0x0001 max_op_sys_clk_div (RO) Maximum divisor for the output sys_clk. Read-only. 15:0 0x43C0 min_op_sys_clk_freq_mhz_1 (RO) FLP32. Minimum frequency for output sys_clk is 10 MHz. Read-only. 15:0 0x0000 min_op_sys_clk_freq_mhz_2 (RO) FLP32. Minimum frequency for output sys_clk is 10 MHz. Read-only. 15:0 0x4440 max_op_sys_clk_freq_mhz_1 (RO) FLP32. Maximum frequency for output sys_clk is 92 MHz. Read-only. 15:0 0x0000 max_op_sys_clk_freq_mhz_2 (RO) FLP32. Maximum frequency for output sys_clk is 92 MHz. Read-only. 15:0 0x0008 min_op_pix_clk_div (RO) N N N N N N N N N N N N N N Minimum divisor for output pix_clk. Read-only. Legal values for op_pix_clk_div are 0x01, 0x02 and 0x04. 15:0 0x0008 N N max_op_pix_clk_div (RO) Maximum divisor for output pix_clk. Read-only. Legal values for op_pix_clk_div are 0x01, 0x02 and 0x04. 15:0 0x4240 N N min_op_pix_clk_freq_mhz_1 (RO) FLP32. Minimum frequency for output pix_clk is 5 MHz. Read-only. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 19: Reg. # R4466 R0x1172 R4468 R0x1174 R4470 R0x1176 R4480 R0x1180 R4482 R0x1182 R4484 R0x1184 R4486 R0x1186 R4544 R0x11C0 R4546 R0x11C2 R4548 R0x11C4 R4550 R0x11C6 1: SMIA Parameter Limits (continued) Bits 15:0 Default 0x0000 Name min_op_pix_clk_freq_mhz_2 (RO) Frame Sync'd N N N N N N N N Bad Frame N N N N N N N N N N N FLP32. Minimum frequency for output pix_clk is 5 MHz. Read-only. 15:0 0x42C0 max_op_pix_clk_freq_mhz_1 (RO) FLP32. Maximum frequency for output pix_clk is 92 MHz. Read-only. 15:0 0x0000 max_op_pix_clk_freq_mhz_2 (RO) FLP32. Maximum frequency for output pix_clk is 92 MHz. Read-only. 15:0 0x0000 x_addr_min (RO) Minimum value for x_addr_start, x_addr_end. Read-only. 15:0 0x0000 y_addr_min (RO) Minimum value for y_addr_start, y_addr_end. Read-only. 15:0 0x0CCF x_addr_max (RO) Maximum value for x_addr_start, x_addr_end. Read-only. 15:0 0x099F y_addr_max (RO) Maximum value for y_addr_start, y_addr_end. Read-only. 15:0 0x0001 min_even_inc (RO) Minimum value for increment of even X/Y addresses when subsampling is enabled. Read-only. 15:0 0x0001 N max_even_inc (RO) Maximum value for increment of even X/Y addresses when subsampling is enabled. Read-only. 15:0 0x0001 N min_odd_inc (RO) Minimum value for increment of odd X/Y addresses when subsampling is enabled. Read-only. 15:0 0x0003 N max_odd_inc (RO) R4608 R0x1200 R4614 R0x1206 R4616 R0x1208 R4618 R0x120A R4864 R0x1300 R5120 R0x1400 R5122 R0x1402 R5124 R0x1404 Maximum value for increment of odd X/Y addresses when subsampling is enabled. Read-only. This set of 4 registers declares the capability for the subsampling mode that was called "skip2" and "skip4" on earlier Micron Imaging sensors. Note that this value should have been 3, since only values of 1, 3 and 7 are supported. 15:0 0x0002 N N scaling_capability (RO) Indicates the provision of a full (horizontal and vertical) scaler. Read-only. Indicates the minimum M value for the scaler. Read-only. 15:0 0x0080 scaler_m_max (RO) Indicates the maximum M value for the scaler. Read-only. 15:0 0x0010 scaler_n_min (RO) Indicates the minimum N value for the scaler. Read-only. 15:0 0x0010 scaler_n_max (RO) Indicates the maximum N value for the scaler. Read-only. 15:0 0x0001 compression_capability (RO) N N N N N N N N N N N Indicates the capability for performing 12/10-bit to 8-bit pixel data compression. Read-only. 15:0 0x0242 N matrix_element_RedInRed (RW) Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0xFF00 matrix_element_GreenInRed (RW) N Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0xFFBE N matrix_element_BlueInRed (RW) Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 19: Reg. # R5126 R0x1406 R5128 R0x1408 R5130 R0x140A R5132 R0x140C R5134 R0x140E R5136 R0x1410 1: SMIA Parameter Limits (continued) Bits 15:0 Default 0xFFB4 Name matrix_element_RedInGreen (RW) Frame Sync'd N Bad Frame N N N N N N Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0200 N matrix_element_GreenInGreen (RW) Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0xFF4D N matrix_element_BlueInGreen (RW) Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0xFFF1 N matrix_element_RedInBlue (RW) Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0xFF34 N matrix_element_GreenInBlue (RW) Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x01DC N matrix_element_BlueInBlue (RW) Color-correction matrix. Read-only. Can be made read/write by clearing R0x301A-B[3]. Table 20: Reg. # R12288 R0x3000 R12290 R0x3002 R12292 R0x3004 R12294 R0x3006 R12296 R0x3008 R12298 R0x300A R12300 R0x300C R12304 R0x3010 3: Manufacturer Specific Bits 15:0 Default 0x2B00 Name model_id_ (RW) Frame Sync'd N Y Bad Frame N YM Model ID. Read-only. Can be made read/write by clearing R0x301A-B[3]. 15:0 0x0008 y_addr_start_ (RW) The first row of visible pixels to be read out (not counting any dark rows that may be read). To move the image window, set this register to the starting Y value. 15:0 0x0000 Y N x_addr_start_ (RW) The first column of visible pixels to be read out (not counting any dark columns that may be read). To move the image window, set this register to the starting X value. 15:0 0x0997 Y YM y_addr_end_ (RW) The last row of visible pixels to be read out. 15:0 0x0CBF x_addr_end_ (RW) The last column of visible pixels to be read out. 15:0 0x0A00 frame_length_lines_ (RW) Y Y N YM The number of complete lines (rows) in the output frame. This includes visible lines and vertical blanking lines. 15:0 0x199E Y YM line_length_pck_ (RW) The number of pixel clock periods in one line (row) time. This includes visible pixels and horizontal blanking time. 15:0 0x0100 N Y fine_correction (RW) Fine integration time correction factor. This is an offset that is applied to the programmed value of fine_integration_time such that the actual integration time matches the integration time equation. This register should not be modified under normal operation, but must be modified when binning is enabled. 15:0 0x0010 Y N coarse_integration_time_ (RW) Integration time specified in multiples of line_length_pck_. 15:0 0x056A fine_integration_time_ (RW) Integration time specified as a number of pixel clocks. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. R12306 R0x3012 R12308 R0x3014 Y N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 64 Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12310 R0x3016 3: Manufacturer Specific (continued) Bits 15:0 15:11 10:8 Default 0x0111 X 0x0001 Reserved Output Clock Speed Slows down the output pixel clock frequency relative to the system clock frequency. A programmed value of N gives a output pixel clock period of N system clocks. Only values 1, 2 and 4 are supported. A value of 0 is illegal: it causes the clock to stop. Reserved Output Clock Delay Number of half-system-clock-cycle increments to delay the rising edge of PIXCLK relative to transitions on FRAME_VALID, LINE_VALID, and DOUT. Reserved Pixel Clock Speed Slows down the pixel clock frequency relative to the system clock frequency. A programmed value of N gives a pixel clock period of N system clocks. Only values 1, 2 and 4 are supported. A value of 0 is illegal: it causes the clock to stop. extra_delay (RW) N N Name row_speed (RW) Frame Sync'd Bad Frame 7 6:4 X 0x0001 N N 3 2:0 X 0x0001 Y YM R12312 R0x3018 15:0 0x0000 Y N R12314 R0x301A Extra blanking inserted between frames. A programmed value of N increases the vertical blanking time by N pixel clock periods. Can be used to get a more exact frame rate. May affect the integration times of parts of the image when the integration time is less than 1 frame. 15:0 0x0058 reset_register (RW) N N 15 0x0000 grouped parameter hold 0 = Update of many of the registers is synchronized to frame start. 1 = Inhibit register updates; register changes will remain pending until this bit is returned to 0. When this bit is returned to 0, all pending register updates will be made on the next frame start. Reserved Reserved Not used. Reserved N N 14:13 12 11 X 0x0000 X PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12314 R0x301A 3: Manufacturer Specific (continued) Bits 10 Default 0x0000 Name Restart Bad Frames 1 = a restart is forced any time a bad frame is detected. This can shorten the delay when waiting for a good frame, since the delay for masking out a bad frame will be the integration time rather than the full-frame time. Mask Bad Frames 0 = The sensor will produce bad (corrupted) frames as a result of some register changes. 1 = Bad (corrupted) frames are masked within the sensor by extending the vertical blanking time for the duration of the bad frame. GPI Enable 0 = the primary input buffers associated with the GPI0, GPI1, GPI2, GPI3 inputs are powered down and the GPI cannot be used. 1 = the input buffers are enabled and can be read through R0x30267. Parallel Enable 0 = The parallel data interface (DOUT[11:0], LINE_VALID, FRAME_VALID, and PIXCLK) is disabled and the outputs are placed in a HIGH-Z. 1 = The parallel data interface is enabled. The output signals can be switched between a driven and a HIGH-Z using output-enable control. Drive Pins 0 = The parallel data interface (DOUT[11:0], LINE_VALID, FRAME_VALID, and PIXCLK) may enter a HIGH-Z (depending upon the configuration of R0x3026). 1 = The parallel data interface is driven. This bit is "don't-care" unless bit[7]=1. Frame Sync'd N Bad Frame N 9 0x0000 N N 8 0x0000 N N 7 0x0000 N N 6 0x0001 N N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12314 R0x301A 3: Manufacturer Specific (continued) Bits 5 4 Default X 0x0001 Reserved Standby EOF 0 = Transition to standby is synchronized to the end of a sensor row readout (held-off until LINE_VALID has fallen). 1 = Transition to standby is synchronized to the end of a frame. Lock Reg Many SMIA registers that are specified as read-only are actually implemented as read/write registers. Clearing this bit allows such registers to be written. Stream Setting this bit places the sensor in streaming mode. Clearing this bit places the sensor in a low power mode. The result of clearing this bit depends upon the operating mode of the sensor. Entry and exit from streaming mode can also be controlled from the signal interface. Restart This bit always reads as "0." Setting this bit causes the sensor to truncate the current frame at the end of the current row and start resetting (integrating) the first row. The delay before the first valid frame is read out is equal to the integration time. Reset This bit always reads as "0." Setting this bit initiates a reset sequence: the frame being generated will be truncated. mode_select_ (RW) N Y Name Frame Sync'd Bad Frame 3 0x0001 N N 2 0x0000 Y N 1 0x0000 N Y 0 0x0000 N Y R12316 R0x301C R12317 R0x301D 7:0 0x0000 Y N This bit is an alias of R0x301A-B[2]. 7:0 0x0000 image_orientation_ (RW) 7:2 X Reserved 1 0 0x0000 0x0000 Vertical Flip This bit is an alias of R0x3040[1]. Horizontal Mirror This bit is an alias of R0x3040[0]. Y Y YM YM PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12318 R0x301E R12321 R0x3021 R12322 R0x3022 R12323 R0x3023 R12324 R0x3024 3: Manufacturer Specific (continued) Bits 15:0 Default 0x00A8 Name data_pedestal_ (RW) Frame Sync'd N Bad Frame Y Constant offset that is added to the ADC output for all visible pixels in order to set the black level to a value greater than 0. Read-only. Can be made read/write by clearing R0x301A-B[3]. 7:0 0x0000 N Y software_reset_ (RW) This bit is an alias of R0x301A-B[0]. 7:0 0x0000 grouped_parameter_hold_ (RW) This bit is an alias of R0x301A-B[15]. 7:0 0x0000 mask_corrupted_frames_ (RW) This bit is an alias of R0x301A-B[9]. 7:0 0x0000 pixel_order_ (RO) 00 = First row is GreenR/Red, first pixel is GreenR 01 = First row is GreenR/Red, first pixel is Red 02 = First row is Blue/GreenB, first pixel is Blue 03 = First row is Blue/GreenB, first pixel is GreenB The value in this register changes as a function of R0x3040[1:0]. 15:0 0xFFFF gpi_status (RW) 15:13 0x0007 Standby Pin Select Associate the standby function with an active-high input pin 0 = associate with GPI0 1 = associate with GPI1 2 = associate with GPI2 3 = associate with GPI3 4-6 = RESERVED 7 = standby function cannot be controlled by any pin Must be set to 7 if reset[8]=0. N N N N N N R12326 R0x3026 N N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12326 R0x3026 3: Manufacturer Specific (continued) Bits 12:10 Default 0x0007 Name OE_N Pin Select Associate the output-enable function with an active-low input pin 0 = associate with GPI0 1 = associate with GPI1 2 = associate with GPI2 3 = associate with GPI3 4-6 = RESERVED 7 = output-enable function is not controlled by any pin Must be set to 7 if reset[8]=0. S Trigger Pin Select Associate the trigger function with an active-high input pin 0 = associate with GPI0 1 = associate with GPI1 2 = associate with GPI2 3 = associate with GPI3 4-6 = RESERVED 7 = Trigger function is not controlled by any pin Must be set to 7 if R0x301A-B[8]=0. SADDR Pin Select Associate the SADDR function with an active-high input pin 0 = associate with GPI0 1 = associate with GPI1 2 = associate with GPI2 3 = associate with GPI3 4-6 = RESERVED 7 = SADDR function is not controlled by any pin Must be set to 7 if R0x301A-B[8]=0. GPI3 Read-only. Return the current state of the GPI3 input pin. Invalid if R0x301A-B[8]=0. GPI2 Read-only. Return the current state of the GPI2 input pin. Invalid if R0x301A-B[8]=0. GPI1 Read-only. Return the current state of the GPI1 input pin. Invalid if R0x301A-B[8]=0. Frame Sync'd N Bad Frame N 9:7 0x0007 N N 6:4 0x0007 N N 3 RO N N 2 RO N N 1 RO N N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12326 R0x3026 3: Manufacturer Specific (continued) Bits 0 Default RO Name GPI0 Read-only. Return the current state of the GPI0 input pin. Invalid if R0x301A-B[8]=0. analogue_gain_code_global_ (RW) Frame Sync'd N Bad Frame N R12328 R0x3028 15:0 0x000D Y N R12330 R0x302A R12332 R0x302C R12334 R0x302E R12336 R0x3030 R12338 R0x3032 R12340 R0x3034 R12342 R0x3036 R12344 R0x3038 R12346 R0x303A R12347 R0x303B Writing a gain code to this register is equivalent to writing that code to each of the 4 color-specific gain code registers. Reading from this register returns the value most recently written to the analogue_gain_code_greenR register. 15:0 0x000D Y N analogue_gain_code_greenR_ (RW) The gain code written to this register sets the gain for green pixels on red/green rows of the pixel array. 15:0 0x000D Y N analogue_gain_code_red_ (RW) The gain code written to this register sets the gain for red pixels. 15:0 0x000D analogue_gain_code_blue_ (RW) The gain code written to this register sets the gain for blue pixels. 15:0 0x000D analogue_gain_code_greenB_ (RW) Y Y N N The gain code written to this register sets the gain for green pixels on blue/green rows of the pixel array. 15:0 0x0100 Y N digital_gain_greenR_ (RW) Digital gain applied to green pixels on red/green rows of the pixel array. The value is an unsigned 8.8 fixed-point format. Bits [10:8] are significant and are an alias of R0x3056[11:9]. 15:0 0x0100 Y N digital_gain_red_ (RW) Digital gain applied to red pixels of the pixel array. The value is an unsigned 8.8 fixed-point format. Bits [10:8] are significant and are an alias of R0x305A[11:9]. 15:0 0x0100 Y N digital_gain_blue_ (RW) Digital gain applied to blue pixels of the pixel array. The value is an unsigned 8.8 fixed-point format. Bits [10:8] are significant and are an alias of R0x3058[11:9]. 15:0 0x0100 Y N digital_gain_greenB_ (RW) Digital gain applied to green pixels on blue/green rows of the pixel array. The value is an unsigned 8.8 fixed-point format. Bits [10:8] are significant and are an alias of R0x305C[11:9]. 7:0 0x000A N N smia_version_ (RO) Return the value 10 to indicate an implementation of revision 1.0 of the SMIA specification. Read-only. 7:0 0x00FF Y N frame_count_ (RO) In the soft standby state this counter is set to 0xFF. In the streaming state this counter increments by 1 (modulo 255) at the start of each frame. The counter is incremented for both good frames and bad (corrupted) frames - its behavior is not affected by the state of R0x301A-B[9] (mask_corrupted_frames). After entry to the streaming state, the first frame will show a frame count of 0x01 in its embedded data. Read-only. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 70 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12348 R0x303C 3: Manufacturer Specific (continued) Bits 15:0 15:2 1 Default 0x0000 X RO Reserved Standby status This bit tells you whether the sensor is in standby state. Can be polled after standby is entered to see when the real low-power state is entered; which can happen at the end of row or frame depending on bit 0x301A[4]. The bit actually reflects the internal signal standby_gated. Framesync Set on register write and reset on framesync. Acts as debug flag to verify that register writes completed before last framesync. read_mode (RW) Special LINE_VALID This feature is not working. Keep setting at 00. 00 = Normal behavior of LINE_VALID 01 = LINE_VALID is driven continuously (continue generating LINE_VALID during vertical blanking) 10 = LINE_VALID is driven continuously as LINE_VALID XOR FRAME_VALID. Reserved Binning summing Enable summing mode for binning. x bin enable Enable analogue binning in X (column) direction. When set, x_odd_inc must be set to 3 or 7 and y_odd_inc must be set to 1, along with other register changes. xy bin enable Enable analogue binning in X and Y (column and row) directions. When set, x_odd_inc and y_odd_inc must be set to 3 or 7, along with other register changes. N N Name frame_status (RO) Frame Sync'd Bad Frame 0 RO N N R12352 R0x3040 15:0 15:14 0x0024 0x0000 N N 13 12 11 X 0x0000 0x0000 Y Y N N 10 0x0000 Y N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 71 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12352 R0x3040 3: Manufacturer Specific (continued) Bits 9 Default 0x0000 Name Low power mode Enables low power mode. This will automatically half the pixel clock speed. Can not be used when pc_speed[2:0] = 4. Reserved X odd increment Increment applied to odd addresses in X (column) direction. 1= Normal readout 3 = Read out alternate pixel pairs to halve the amount of horizontal data in a frame. 7 = Read out 1 of 4 pixel pairs to reduce the amount of horizontal data in a frame by 4. Y odd increment Increment applied to odd addresses in Y (row) direction. 1= Normal readout 3 = Read out alternate pixel pairs to halve the amount of vertical data in a frame. 7 = Read out 1 of 4 pixel pairs to reduce the amount of vertical data in a frame by 4. Vertical Flip 0 = Normal readout 1 = Readout is flipped (mirrored) vertically so that the row specified by y_addr_end_ is read out of the sensor first. Setting this bit will change the bayer pixel order (see R0x3024). Horizontal Mirror 0 = Normal readout 1 = Readout is mirrored horizontally so that the column specified by x_addr_end_ is read out of the sensor first. Setting this bit will change the bayer pixel order (see R0x3024). Frame Sync'd Y Bad Frame YM 8 7:5 X 0x0001 Y YM 4:2 0x0001 Y YM 1 0x0000 Y YM 0 0x0000 Y YM PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 72 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12358 R0x3046 3: Manufacturer Specific (continued) Bits 15:0 15 Default 0x0600 RO flash (RW) Strobe Reflects the current state of the FLASH output signal. Read-only. Triggered Indicates that the FLASH output signal was asserted for the current frame. Read-only. Xenon Flash Enable Xenon flash. When set, the FLASH output signal will assert for the programmed period (bits [7:0]) during vertical blanking. This is achieved by keeping the integration time equal to one frame, and the pulse width less than the vertical blanking time. Frame Delay Flash pulse delay measured in frames. End of Reset 1 = In Xenon mode, the flash is triggered after resetting a frame. 0 = In Xenon mode, the flash is triggered after a frame readout. Every Frame 1 = Flash should be enabled every frame. 0 = Flash should be enabled for 1 frame only. LED Flash Enable LED flash. When set, the FLASH output signal will assert prior to the start of the resetting of a frame and will remain asserted until the end of the frame readout. Reserved flash_count (RW) N N Name Frame Sync'd Bad Frame 14 RO N N 13 0x0000 Y N 12:11 0x0000 N N 10 0x0001 N N 9 0x0001 N N 8 0x0000 Y Y R12360 R0x3048 7:0 15:0 X 0x0008 N N Length of flash pulse when Xenon flash is enabled. The value specifies the length in units of 256 x PIXCLK cycle increments (by default, PIXCLK = system_clock). When the Xenon count is set to its maximum value (0x3FF), the flash pulse will automatically be truncated prior to the readout of the first row, giving the longest pulse possible. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 73 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12374 R0x3056 3: Manufacturer Specific (continued) Bits 15:0 15:12 11:9 8:7 Default 0x0234 X 0x0001 0x0000 Reserved Digital Gain Digital Gain. Legal values 1-7. Analog Gain Analog gain = (bit [8] + 1) * (bit [7] + 1) * initial gain. Initial Gain Initial gain = bits [6:0] * 1/32. blue_gain (RW) Reserved Digital Gain Digital Gain. Legal values 1-7. Analog Gain Analog gain = (bit [8] + 1) * (bit [7] + 1) * initial gain. Initial Gain Initial gain = bits [6:0] * 1/32. red_gain (RW) Reserved Digital Gain Digital Gain. Legal values 1-7. Analog Gain Analog gain = (bit [8] + 1) * (bit [7] + 1) * initial gain. Initial Gain Initial gain = bits [6:0] * 1/32. green2_gain (RW) Reserved Digital Gain Digital Gain. Legal values 1-7. Analog Gain Analog gain = (bit [8] + 1) * (bit [7] + 1) * initial gain. Initial Gain Initial gain = bits [6:0] * 1/32. global_gain (RW) Y Y N N Y Y N N Y Y N N Y Y N N Name green1_gain (RW) Frame Sync'd Bad Frame 6:0 R12376 R0x3058 15:0 15:12 11:9 8:7 0x0034 0x0234 X 0x0001 0x0000 Y N 6:0 R12378 R0x305A 15:0 15:12 11:9 8:7 0x0034 0x0234 X 0x0001 0x0000 Y N 6:0 R12380 R0x305C 15:0 15:12 11:9 8:7 0x0034 0x0234 X 0x0001 0x0000 Y N 6:0 R12382 R0x305E R12394 R0x306A 15:0 0x0034 0x0234 Y Y N N Writing a gain to this register is equivalent to writing that code to each of the 4 color-specific gain registers. Reading from this register returns the value most recently written to the green1_gain register. 15:0 0x0000 datapath_status (RW) 15:5 X Reserved 4 0x0000 Reserved Reserved N N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 74 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12394 R0x306A 3: Manufacturer Specific (continued) Bits 3 Default 0x0000 Name Frame time exceeded If the y_output_size is so large that the total number of lines output on the odp exceeds the total number of lines allowed by frame_length_lines, the "frame time exceeded" error will be flagged. The general solution to this error is to reduce y_output_size to match the size of the frame being generated by the sensor_core. Once this bit is set, the condition that caused the error must be cleared, then write a "1" to this bit position to clear it. Line time exceeded If the odp clock rate and x_output_size do not allow an output line to be generated within the time allowed by line_length_pck, the "line time exceeded" error will be flagged. The general solution to this error is first to reduce x_output_size to match the size of the frame being generated by the sensor_core and then (if necessary) increase line_length_pck to allow time for the output line. Once this bit is set, the condition that caused the error must be cleared, then write a "1" to this bit position to clear it. Frame Sync'd N Bad Frame N 2 0x0000 N N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 75 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12394 R0x306A 3: Manufacturer Specific (continued) Bits 1 Default 0x0000 Name FIFO overflow If the odp data rate is lower than the sensor_core data rate and x_output_size is large enough, the output buffer can overflow, and the "FIFO overflow" error will be flagged. The FIFO is sized to accommodate a full-sizeframe from the sensor core, so this error can only occur when x_output_size is unnecessarily large. The general solution to this error is to reduce x_output_size. Once this bit is set, the condition that caused the error must be cleared, then write a "1" to this bit position to clear it. FIFO underflow If the output buffer underflows, the "FIFO underflow" error will be flagged. There is no known setup scenario that will stimulate this error. Once this bit is set, you must clear the condition that caused the error then write a "1" to this bit position to clear it. datapath_select (RW) Slew-rate control Parallel Interface Selects the slew (edge) rate for the DOUT[11:0], SHUTTER, FRAME_VALID, LINE_VALID and FLASH outputs. Only affects SHUTTER and FLASH outputs when parallel data output is disabled. The value 7 results in the fastest edge rates on these signals. Slowing down the edge rate can reduce ringing and electromagnetic emissions. Slew-rate control PIXCLK Selects the slew (edge) rate for the PIXCLK output. Has no effect when parallel data output is disabled. The value 7 results in the fastest edge rates on this signal. Slowing down the edge rate can reduce ringing and electromagnetic emissions. Frame Sync'd N Bad Frame N 0 0x0000 N N R12398 R0x306E 15:0 15:13 0x9080 0x0004 N N 12:10 0x0004 N N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 76 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12398 R0x306E 3: Manufacturer Specific (continued) Bits 9:8 7 Default X 0x0001 Reserved Profile SMIA profile mode. Should only be changed in standby, and with attention to other clock settings. 0 = Profile 0 1 = Profile 1/2. Reserved True Bayer mode Enables true Bayer scaling mode. Reserved test_pattern_mode_ (RW) N Y Name Frame Sync'd Bad Frame 6:5 4 3:0 15:0 X 0x0000 X 0x0000 N N R12400 R0x3070 N Y R12402 R0x3072 R12404 R0x3074 R12406 R0x3076 R12408 R0x3078 R12448 R0x30A0 R12450 R0x30A2 R12452 R0x30A4 R12454 R0x30A6 0 = Normal operation: Generate output data from pixel array 1 = Solid colour test pattern. 2 = 100% colour bar test pattern 3 = Fade to grey colour bar test pattern 4 = PN9 Link integrity test pattern 256 = Marching 1's test pattern other = Reserved. 15:0 0x0000 test_data_red_ (RW) N Y The value for red pixels in the bayer data used for the solid colour test pattern and the test cursors. 15:0 0x0000 N Y test_data_green1_ (RW) The value for green pixels in red/green rows of the bayer data used for the solid colour test pattern and the test cursors. 15:0 0x0000 N Y test_data_blue_ (RW) The value for blue pixels in the bayer data used for the solid colour test pattern and the test cursors. 15:0 0x0000 N Y test_data_green2 (RW) The value for green pixels in blue/green rows of the bayer data used for the solid colour test pattern and the test cursors. 15:0 0x0001 N N x_even_inc_ (RO) Read-only. 15:0 0x0001 x_odd_inc_ (RW) Y N Y YM N YM This register field is an alias of R0x3040[7:5] 15:0 0x0001 y_even_inc_ (RO) Read-only. 15:0 0x0001 y_odd_inc_ (RW) This register field is an alias of R0x3040[4:2] PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 77 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12640 R0x3160 3: Manufacturer Specific (continued) Bits 15:0 15:10 9 Default 0x0000 X RO Name global_seq_trigger (RW) Reserved Grst Rd Read-Only. Global reset read sequence indicator. Grst Sequence Read-only. Global reset sequence indicator. Reserved Global Flash 0 = When a global reset sequence is triggered, the FLASH output will remain negated. 1 = When a global reset sequence is triggered, the FLASH output will pulse during the integration phase. Global Bulb 0 = Shutter open is triggered from bit[0] and shutter close is timed from the trigger point. 1 = Shutter open and close are triggered from bit[0]. This corresponds to the shutter "B" setting on a traditional camera, where "B" originally stood for "Bulb" (the shutter setting used for synchronization with a magnesium foil flash bulb) and was later considered to stand for "Brief" (an exposure that was longer than the shutter could automatically accommodate). Global Trigger When bit[1]=0, a 0-to-1 transition of this bit initiates (triggers) a global reset sequence. When bit[1]=1, a 0-to-1 transition of this bit initiates a global reset sequence, and leaves the shutter open; a 1-to-0 transition of this bit closes the shutter. These operations can also be controlled from the signal interface by enabling one of the GPI[3:0] signals as a trigger input. global_rst_end (RW) Frame Sync'd Bad Frame N N 8 RO N N 7:3 2 X 0x0000 N Y 1 0x0000 N Y 0 0x0000 N Y R12642 R0x3162 15:0 0x0050 N N Controls the duration of the global reset row reset phase. A value of N gives a duration of N * 512 / vt_pix_clk_freq_mhz. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 78 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R12644 R0x3164 3: Manufacturer Specific (continued) Bits 15:0 Default 0x0078 Name global_shutter_start (RW) Frame Sync'd N Bad Frame N R12646 R0x3166 Controls the delay before the assertion of the SHUTTER output during a global reset sequence. A value of N gives an assertion time of N * 512 / vt_pix_clk_freq_mhz timed from the end of row that was in progress when the global reset sequence was triggered. 15:0 0x00A0 N N global_read_start (RW) Controls the delay before the start of the global reset readout phase (equivalent to the end of global reset integration phase). A value of N gives a delay of N * 512 / vt_pix_clk_freq_mhz. The integration time is given by (global_read_start - global_rst_end) * 512 / vt_pix_clk_freq_mhz. N N 15:0 0x0000 horizontal_cursor_position_ (RW) Specify the start column for the test cursor. 15:0 0x0000 vertical_cursor_position_ (RW) Specify the start column for the test cursor. 15:0 0x0000 horizontal_cursor_width_ (RW) N N N N N N N N N N N N N N N N N N R12776 R0x31E8 R12778 R0x31EA R12780 R0x31EC R12782 R0x31EE R12796 R0x31FC R13824 R0x3600 R13826 R0x3602 R13828 R0x3604 R13830 R0x3606 R13832 R0x3608 R13834 R0x360A R13836 R0x360C R13838 R0x360E R13840 R0x3610 R13842 R0x3612 R13844 R0x3614 R13846 R0x3616 Specify the width, in rows, of the horizontal test cursor. A width of 0 disables the cursor. 15:0 0x0000 N vertical_cursor_width_ (RW) Specify the width, in columns, of the vertical test cursor. A width of 0 disables the cursor. 15:0 0x03020 N i2c_ids I2C address registers. 15:0 0x0000 P0 coefficient for Q0 for Gr. 15:0 0x0000 15:0 0x0000 P_GR_P0Q0 (RW) P_GR_P0Q1 (RW) P_GR_P0Q2 (RW) P_GR_P0Q3 (RW) P_GR_P0Q4 (RW) P_RD_P0Q0 (RW) P_RD_P0Q1 (RW) P_RD_P0Q2 (RW) P_RD_P0Q3 (RW) P_RD_P0Q4 (RW) P_BL_P0Q0 (RW) P_BL_P0Q1 (RW) N N N N N N N N N N N N P0 coefficient for Q2 for Gr. 15:0 0x0000 P0 coefficient for Q3 for Gr. 15:0 0x0000 P0 coefficient for Q4 for Gr. 15:0 0x0000 P0 coefficient for Q0 for Rd. 15:0 0x0000 P0 coefficient for Q1 for Rd. 15:0 0x0000 P0 coefficient for Q2 for Rd. 15:0 0x0000 P0 coefficient for Q3 for Rd. 15:0 0x0000 P0 coefficient for Q4 for Rd. 15:0 0x0000 P0 coefficient for Q0 for Bl. 15:0 0x0000 P0 coefficient for Q1 for Bl. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 79 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R13848 R0x3618 R13850 R0x361A R13852 R0x361C R13854 R0x361E R13856 R0x3620 R13858 R0x3622 R13860 R0x3624 R13862 R0x3626 R13888 R0x3640 R13890 R0x3642 R13892 R0x3644 R13894 R0x3646 R13896 R0x3648 R13898 R0x364A R13900 R0x364C R13902 R0x364E R13904 R0x3650 R13906 R0x3652 R13908 R0x3654 R13910 R0x3656 R13912 R0x3658 3: Manufacturer Specific (continued) Bits 15:0 Default 0x0000 Name P_BL_P0Q2 (RW) P_BL_P0Q3 (RW) P_BL_P0Q4 (RW) P_GB_P0Q0 (RW) P_GB_P0Q1 (RW) P_GB_P0Q2 (RW) P_GB_P0Q3 (RW) P_GB_P0Q4 (RW) P_GR_P1Q0 (RW) P_GR_P1Q1 (RW) P_GR_P1Q2 (RW) P_GR_P1Q3 (RW) P_GR_P1Q4 (RW) P_RD_P1Q0 (RW) P_RD_P1Q1 (RW) P_RD_P1Q2 (RW) P_RD_P1Q3 (RW) P_RD_P1Q4 (RW) P_BL_P1Q0 (RW) P_BL_P1Q1 (RW) P_BL_P1Q2 (RW) Frame Sync'd N N N N N N N N N N N N N N N N N N N N N Bad Frame N N N N N N N N N N N N N N N N N N N N N P0 coefficient for Q2 for Bl. 15:0 0x0000 P0 coefficient for Q3 for Bl. 15:0 0x0000 P0 coefficient for Q4 for Bl. 15:0 0x0000 P0 coefficient for Q0 for Gb. 15:0 0x0000 P0 coefficient for Q1 for Gb. 15:0 0x0000 P0 coefficient for Q2 for Gb. 15:0 0x0000 P0 coefficient for Q3 for Gb. 15:0 0x0000 P0 coefficient for Q4 for Gb. 15:0 0x0000 P1 coefficient for Q0 for Gr. 15:0 0x0000 P1 coefficient for Q1 for Gr. 15:0 0x0000 P1 coefficient for Q2 for Gr. 15:0 0x0000 P1 coefficient for Q3 for Gr. 15:0 0x0000 P1 coefficient for Q4 for Gr. 15:0 0x0000 P1 coefficient for Q0 for Rd. 15:0 0x0000 P1 coefficient for Q1 for Rd. 15:0 0x0000 P1 coefficient for Q2 for Rd. 15:0 0x0000 P1 coefficient for Q3 for Rd. 15:0 0x0000 P1 coefficient for Q4 for Rd. 15:0 0x0000 P1 coefficient for Q0 for Bl. 15:0 0x0000 P1 coefficient for Q1 for Bl. 15:0 0x0000 P1 coefficient for Q2 for Bl. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 80 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R13914 R0x365A R13916 R0x365C R13918 R0x365E R13920 R0x3660 R13922 R0x3662 R13924 R0x3664 R13926 R0x3666 R13952 R0x3680 R13954 R0x3682 R13956 R0x3684 R13958 R0x3686 R13960 R0x3688 R13962 R0x368A R13964 R0x368C R13966 R0x368E R13968 R0x3690 R13970 R0x3692 R13972 R0x3694 R13974 R0x3696 R13976 R0x3698 R13978 R0x369A 3: Manufacturer Specific (continued) Bits 15:0 Default 0x0000 Name P_BL_P1Q3 (RW) P_BL_P1Q4 (RW) P_GB_P1Q0 (RW) P_GB_P1Q1 (RW) P_GB_P1Q2 (RW) P_GB_P1Q3 (RW) P_GB_P1Q4 (RW) P_GR_P2Q0 (RW) P_GR_P2Q1 (RW) P_GR_P2Q2 (RW) P_GR_P2Q3 (RW) P_GR_P2Q4 (RW) P_RD_P2Q0 (RW) P_RD_P2Q1 (RW) P_RD_P2Q2 (RW) P_RD_P2Q3 (RW) P_RD_P2Q4 (RW) P_BL_P2Q0 (RW) P_BL_P2Q1 (RW) P_BL_P2Q2 (RW) P_BL_P2Q3 (RW) Frame Sync'd N N N N N N N N N N N N N N N N N N N N N Bad Frame N N N N N N N N N N N N N N N N N N N N N P1 coefficient for Q3 for Bl. 15:0 0x0000 P1 coefficient for Q4 for Bl. 15:0 0x0000 P1 coefficient for Q0 for Gb. 15:0 0x0000 P1 coefficient for Q1 for Gb. 15:0 0x0000 P1 coefficient for Q2 for Gb. 15:0 0x0000 P1 coefficient for Q3 for Gb. 15:0 0x0000 P1 coefficient for Q4 for Gb. 15:0 0x0000 P2 coefficient for Q0 for Gr. 15:0 0x0000 P2 coefficient for Q1 for Gr. 15:0 0x0000 P2 coefficient for Q2 for Gr. 15:0 0x0000 P2 coefficient for Q3 for Gr. 15:0 0x0000 P2 coefficient for Q4 for Gr. 15:0 0x0000 P2 coefficient for Q0 for Rd. 15:0 0x0000 P2 coefficient for Q1 for Rd. 15:0 0x0000 P2 coefficient for Q2 for Rd. 15:0 0x0000 P2 coefficient for Q3 for Rd. 15:0 0x0000 P2 coefficient for Q4 for Rd. 15:0 0x0000 P2 coefficient for Q0 for Bl. 15:0 0x0000 P2 coefficient for Q1 for Bl. 15:0 0x0000 P2 coefficient for Q2 for Bl. 15:0 0x0000 P2 coefficient for Q3 for Bl. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 81 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R13980 R0x369C R13982 R0x369E R13984 R0x36A0 R13986 R0x36A2 R13988 R0x36A4 R13990 R0x36A6 R14016 R0x36C0 R14018 R0x36C2 R14020 R0x36C4 R14022 R0x36C6 R14024 R0x36C8 R14026 R0x36CA R14028 R0x36CC R14030 R0x36CE R14032 R0x36D0 R14034 R0x36D2 R14036 R0x36D4 R14038 R0x36D6 R14040 R0x36D8 R14042 R0x36DA R14044 R0x36DC 3: Manufacturer Specific (continued) Bits 15:0 Default 0x0000 Name P_BL_P2Q4 (RW) P_GB_P2Q0 (RW) P_GB_P2Q1 (RW) P_GB_P2Q2 (RW) P_GB_P2Q3 (RW) P_GB_P2Q4 (RW) P_GR_P3Q0 (RW) P_GR_P3Q1 (RW) P_GR_P3Q2 (RW) P_GR_P3Q3 (RW) P_GR_P3Q4 (RW) P_RD_P3Q0 (RW) P_RD_P3Q1 (RW) P_RD_P3Q2 (RW) P_RD_P3Q3 (RW) P_RD_P3Q4 (RW) P_BL_P3Q0 (RW) P_BL_P3Q1 (RW) P_BL_P3Q2 (RW) P_BL_P3Q3 (RW) P_BL_P3Q4 (RW) Frame Sync'd N N N N N N N N N N N N N N N N N N N N N Bad Frame N N N N N N N N N N N N N N N N N N N N N P2 coefficient for Q4 for Bl. 15:0 0x0000 P2 coefficient for Q0 for Gb. 15:0 0x0000 P2 coefficient for Q1 for Gb. 15:0 0x0000 P2 coefficient for Q2 for Gb. 15:0 0x0000 P2 coefficient for Q3 for Gb. 15:0 0x0000 P2 coefficient for Q4 for Gb. 15:0 0x0000 P3 coefficient for Q0 for Gr. 15:0 0x0000 P3 coefficient for Q1 for Gr. 15:0 0x0000 P3 coefficient for Q2 for Gr. 15:0 0x0000 P3 coefficient for Q3 for Gr. 15:0 0x0000 P3 coefficient for Q4 for Gr. 15:0 0x0000 P3 coefficient for Q0 for Rd. 15:0 0x0000 P3 coefficient for Q1 for Rd. 15:0 0x0000 P3 coefficient for Q2 for Rd. 15:0 0x0000 P3 coefficient for Q3 for Rd. 15:0 0x0000 P3 coefficient for Q4 for Rd. 15:0 0x0000 P3 coefficient for Q0 for Bl. 15:0 0x0000 P3 coefficient for Q1 for Bl. 15:0 0x0000 P3 coefficient for Q2 for Bl. 15:0 0x0000 P3 coefficient for Q3 for Bl. 15:0 0x0000 P3 coefficient for Q4 for Bl. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 82 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R14046 R0x36DE R14048 R0x36E0 R14050 R0x36E2 R14052 R0x36E4 R14054 R0x36E6 R14080 R0x3700 R14082 R0x3702 R14084 R0x3704 R14086 R0x3706 R14088 R0x3708 R14090 R0x370A R14092 R0x370C R14094 R0x370E R14096 R0x3710 R14098 R0x3712 R14100 R0x3714 R14102 R0x3716 R14104 R0x3718 R14106 R0x371A R14108 R0x371C R14110 R0x371E 3: Manufacturer Specific (continued) Bits 15:0 Default 0x0000 Name P_GB_P3Q0 (RW) P_GB_P3Q1 (RW) P_GB_P3Q2 (RW) P_GB_P3Q3 (RW) P_GB_P3Q4 (RW) P_GR_P4Q0 (RW) P_GR_P4Q1 (RW) P_GR_P4Q2 (RW) P_GR_P4Q3 (RW) P_GR_P4Q4 (RW) P_RD_P4Q0 (RW) P_RD_P4Q1 (RW) P_RD_P4Q2 (RW) P_RD_P4Q3 (RW) P_RD_P4Q4 (RW) P_BL_P4Q0 (RW) P_BL_P4Q1 (RW) P_BL_P4Q2 (RW) P_BL_P4Q3 (RW) P_BL_P4Q4 (RW) P_GB_P4Q0 (RW) Frame Sync'd N N N N N N N N N N N N N N N N N N N N N Bad Frame N N N N N N N N N N N N N N N N N N N N N P3 coefficient for Q0 for Gb. 15:0 0x0000 P3 coefficient for Q1 for Gb. 15:0 0x0000 P3 coefficient for Q2 for Gb. 15:0 0x0000 P3 coefficient for Q3 for Gb. 15:0 0x0000 P3 coefficient for Q4 for Gb. 15:0 0x0000 P4 coefficient for Q0 for Gr. 15:0 0x0000 P4 coefficient for Q1 for Gr. 15:0 0x0000 P4 coefficient for Q2 for Gr. 15:0 0x0000 P4 coefficient for Q3 for Gr. 15:0 0x0000 P4 coefficient for Q4 for Gr. 15:0 0x0000 P4 coefficient for Q0 for Rd. 15:0 0x0000 P4 coefficient for Q1 for Rd. 15:0 0x0000 P4 coefficient for Q2 for Rd. 15:0 0x0000 P4 coefficient for Q3 for Rd. 15:0 0x0000 P4 coefficient for Q4 for Rd. 15:0 0x0000 P4 coefficient for Q0 for Bl. 15:0 0x0000 P4 coefficient for Q1 for Bl. 15:0 0x0000 P4 coefficient for Q2 for Bl. 15:0 0x0000 P4 coefficient for Q3 for Bl. 15:0 0x0000 P4 coefficient for Q4 for Bl. 15:0 0x0000 P4 coefficient for Q0 for Gb. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 83 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Register Description Table 20: Reg. # R14112 R0x3720 R14114 R0x3722 R14116 R0x3724 R14118 R0x3726 R14208 R0x3780 3: Manufacturer Specific (continued) Bits 15:0 Default 0x0000 Name P_GB_P4Q1 (RW) P_GB_P4Q2 (RW) P_GB_P4Q3 (RW) P_GB_P4Q4 (RW) SC_ENABLE (WO) Enable LC Reserved Frame Sync'd N N N N Bad Frame N N N N P4 coefficient for Q1 for Gb. 15:0 0x0000 P4 coefficient for Q2 for Gb. 15:0 0x0000 P4 coefficient for Q3 for Gb. 15:0 0x0000 P4 coefficient for Q4 for Gb. 15:0 0x0000 15 0x0000 14:0 X N N R14210 R0x3782 R14212 R0x3784 When SC_ENABLE bit is set, _sc will generate function and correct stream of pixels. When not set, _sc will bypass data. 15:0 0x0000 N N ORIGIN_C (RW) Origin of function: ASpplied as offset to X (col) coordinate of pixel. 15:0 0x0000 ORIGIN_R (RW) Origin of function: Applied as offset to Y (row) coordinate of pixel. N N PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__4reg_desc.fm - Rev. C 10/06 EN 84 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor System States System States The system states of the sensor are represented as a state diagram below and described in subsequent sections. The effect of RESET_BAR on the system state and the configuration of the PLL in the different states are shown in Figure 33. Figure 33: Sensor System States Power supplies turned off (asynchronous from any state) Powered Off Powered On POR = 1 POR active POR = 0 RESET_BAR = 0 Hardware Standby RESET_BAR transitions 1 -> 0 (asynchronous from any state) RESET_BAR = 1 6000 EXTCLK Cycles Internal Initialization Two-wire Serial Interface Write: software_reset=1 Timeout Software Standby PLL not locked Two-wire Seial Interface Write: mode_select=1 PLL Lock Frame in progress PLL locked Streaming Wait For Frame End Two-wire Serial Interface Write: mode_select=0 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 85 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor System States Table 21: RESET_BAR and PLL in System States State Powered off Hardware standby Internal Initialization Software standby PLL Lock Streaming Wait for frame end RESET_BAR x 0 VCO Powered-down 1 VCO powering up and locking, PLL output bypassed VCO running, PLL clock outputs active PLL PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 86 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 34: CRA vs. Image Height Image Height CRA vs. Image Height Plot (%) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 (mm) 0 0.179 0.357 0.536 0.714 0.893 1.071 1.250 1.428 1.607 1.785 1.964 2.142 2.321 2.499 2.678 2.856 3.035 3.213 3.392 3.570 CRA (Deg) 0 0.51 1.02 1.53 2.04 2.55 3.06 3.57 4.08 4.59 5.10 5.60 6.11 6.62 7.13 7.64 8.15 8.66 9.17 9.68 10.19 12 10 8 CRA (deg) 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 Image Height (%) PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 87 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Timing Specifications Timing Specifications Power-up It is recommended to simultaneously apply VDD, VDDIO, and VDDPLL first, followed by VAA and VAAPIX. The maximum time allowed between the first and last voltage applied is 500ms. Reset Two types of reset are available: * A hard reset is issued by toggling RESET_BAR. * A soft reset is issues by writing commands through the serial interface. Hard Reset Figure 35: Hard Reset t1 t2 EXTCLK t4 t3 RESET_BAR SDATA RESET ROM Read Standby/First Serial Write Allowed A hard reset sequence to the camera can be activated by the following steps: 1. Wait for all supplies to be stable. 2. Assert RESET_BAR for at least 30 EXTCLK cycles. 3. De-assert RESET_BAR (input clock must be running for at least 10 EXTCLK cycles). 4. Wait 6000 clock cycles before using the two-wire serial interface. Soft Reset The sensor can be reset under software control by writing "1" to software_reset (R0x0103). A software reset asynchronously resets the sensor, truncating any frame that is in progress; the sensor then starts its internal initialization sequence. At this point, the behavior is exactly the same as for the power-on reset sequence. Signal State during Reset Table 22 shows the state of the signal interface during hardware standby (RESET_BAR asserted) and the default state during software standby (after exit from hardware standby and before any registers within the sensor have been changed from their default power-up values). PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 88 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Timing Specifications Table 22: Signal State During Reset Pad Type Input Input Output Output Output Output Input I/O Output Output Input Input Hardware Standby Enabled. Must be driven to a valid logic level. Enabled. Must be driven to a valid logic level. Software Standby Pad Name EXTCLK RESET_BAR (XSHUTDOWN) LINE_VALID FRAME_VALID DOUT[11:0] PIXCLK SCLK SDATA FLASH SHUTTER GPI[3:0] TEST High-Z. Can be left disconnected/floating. Enabled. Must be pulled-up or driven to a valid logic level. Enabled as an input. Must be pulled-up or driven to a valid logic level. High Z. High Z. Powered down. Can be left disconnected/floating. Enabled. Must be driven to a logic 0. Logic 0 Logic 0 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 89 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Electrical Specifications Electrical Specifications Table 23: Electrical Characteristics and Operating Conditions EXTCLK = 24 MHz; VDD = 1.8V; VDDIO = 1.8V; VAA = 2.8V; VAAPIX = 2.8V; VDDPLL = 2.8V; Temperature (at junction) = 25C; CLOAD = 15pF Symbol VDD VDDIO VAA VAAPIX VDDPLL IDD1 IDDIO1 IDDIO1 IAA1 IAAPIX1 IDDPLL1 IDD2 IDDIO2 IDDIO2 IAA2 IAAPIX2 IDDPLL2 IDD2 IDDIO2 IDDIO2 IAA2 IAAPIX2 IDDPLL2 IDDSTDBY1 IDDIOSTDBY1 IDDIOSTDBY1 IAASTDBY1 IAAPIXSTDBY1 IDDPLLSTDBY1 IDDSTDBY2 IDDIOSTDBY2 IDDIOSTDBY2 IAASTDBY2 IAAPIXSTDBY2 IDDPLLSTDBY2 IDDSTDBY3 IDDIOSTDBY3 Definition Core digital voltage I/O digital voltage Analog voltage Pixel supply voltage PLL supply voltage Digital operating current I/O digital operating current I/O digital operating current Analog operating current Pixel supply current PLL supply current Total Power Consumption Digital operating current I/O digital operating current I/O digital operating current Analog operating current Pixel supply current PLL supply current Total Power Consumption Digital operating current I/O digital operating current I/O digital operating current Analog operating current Pixel supply current PLL supply current Total Power Consumption Digital standby current I/O digital standby current I/O digital standby current Analog standby current Pixel supply standby current PLL standby current Digital standby current I/O digital standby current I/O digital standby current Analog standby current Pixel supply standby current PLL standby current Digital standby current I/O digital standby current Conditions Min 1.7 2.4 2.4 2.4 2.4 2.5 30 10 20 120 0.1 4.0 457 20 5 10 120 0.1 4.0 411 10 5 10 60 0.1 4.0 225 650 5 5 0.0 0 5 5 1.0 1.0 0.0 0 0 650 5 Typ 1.8 1.8 2.8 2.8 2.8 2.8 40 20 35 165 1.5 5.0 650 30 15 20 165 3.0 5.0 594 20 15 20 80 1.5 5.0 334 800 20 35 0.15 0.3 16 20 4 8 0.15 0.3 0.2 800 20 Max 1.9 1.9 3.1 3.1 3.1 3.1 50 30 50 190 7.0 6.5 880 40 25 30 190 7.0 6.5 726 30 25 30 95 7.0 6.5 442 950 30 50 0.5 0.5 25 40 8 15 0.5 0.5 0.4 950 30 Units V V V V V V mA mA mA mA mA mA mW mA mA mA mA mA mA mW mA mA mA mA mA mA mW A A A A A A A A A A A A A A f Snapshot, fullres 11 fps Snapshot VDDIO = 1.8V Snapshot VDDIO = 2.8V Snapshot Snapshot Snapshot Snapshot Preview, binning 30 fps Preview VDDIO = 1.8 Preview VDDIO = 2.8 Preview Preview Preview Preview Low power preview, binning 30 fps Low power preview VDDIO = 1.8 Low power preview VDDIO = 2.8 Preview Low power preview Low power preview Low power preview Hard standby/EXTCLK En Standby/EXTCLK En VDDIO = 1.8 Standby/EXTCLK En VDDIO = 2.8 Standby/EXTCLK En Standby/EXTCLK En Standby/EXTCLK En Hard standby/EXTCLK Dis Standby/EXTCLK Dis VDDIO = 1.8 Standby/EXTCLK Dis VDDIO = 2.8 Standby/EXTCLK Dis Standby/EXTCLK Dis Standby/EXTCLK Dis Soft standby Soft standby VDDIO = 1.8 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 90 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Electrical Specifications Table 23: Electrical Characteristics and Operating Conditions (Continued) EXTCLK = 24 MHz; VDD = 1.8V; VDDIO = 1.8V; VAA = 2.8V; VAAPIX = 2.8V; VDDPLL = 2.8V; Temperature (at junction) = 25C; CLOAD = 15pF Symbol IDDIOSTDBY3 IAASTDBY3 IAAPIXSTDBY3 IDDPLLSTDBY3 Definition I/O digital standby current Analog standby current Pixel supply standby current PLL standby current Conditions Soft standby VDDIO = 2.8 Soft standby Soft standby Soft standby Min 5 0.0 0 5 Typ 35 0.15 .3 35 Max 50 0.5 .5 60 Units A A A A f PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 91 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Electrical Specifications Table 24: I/O Parameters EXTCLK = 24 MHz; VDD = 1.8V; VDDIO = 1.8V; VAA = 2.8V; VAAPIX = 2.8V; VDDPLL = 2.8V; Lighting conditions = 0 lux f Symbols Definition VIH VIH VIL VIL IIN VOH VOL IOH IOL IOZ Input HIGH voltage Input HIGH voltage Input LOW voltage Input LOW voltage Input leakage current Output HIGH voltage Output LOW voltage Output HIGH current Output LOW current Tri-state output leakage current Conditions VDDIO = 1.8V VDDIO = 2.8V VDDIO = 1.8V VDDIO = 2.8V No pull-up resistor; Vin = VDD or DGND At specified IOH At specified IOL At specified VOH At specified VOL Min 1.4 2.4 GND - 0.3 GND - 0.3 -20 VDDIO - 0.4V - - - - Max VDDIO + 0.3 VDDIO + 0.3 0.4 0.8 20 - 0.4 -12 9 10 Units V V V V A V V mA mA A Table 25: Typical Power CIF 500 525 QVGA 500 525 VGA 500 525 UXGA 500 530 QXGA 505 535 QSXGA 505 540 Units mW mW Frame Rate Preview Snapshot PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 92 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor I/O Timing I/O Timing Figure 36: I/O TIming tR 90% 10% tF tEXTCLK EXTCLK PIXCLK tPD tPD Pxl_0 DATA[11:0] XXX XXX Pxl-1 XXX Pxl_2 XXX XXX Pxl_n XXX tPFL tPLL FRAME_VALID/ LINE_VALID tPFH tPLH FRAME_VALID leads LINE_VALID by 6 PIXCLKs. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. Table 26: Symbol fEXTCLK tEXTCLK tR tF tJITTER I/O Timing Definition Input clock frequency Input clock period Input clock rise time Input clock fall time Clock duty cycle Input clock jitter Fastest PIXCLK frequency PIXCLK to data valid PIXCLK to FRAME_VALID HIGH PIXCLK to LINE_VALID HIGH PIXCLK to FRAME_VALID LOW PIXCLK to LINE_VALID LOW Conditions PLL enabled PLL enabled Min 6 166 0.1 0.1 45 - - - - - - - - Typ 24 41 - - 50 - 0.7 96 - - - - - Max 48 20 1 1 55 0.3 - - 3 3 3 3 3 Units MHz ns V/ns V/ns % ns V/ns MHz ns ns ns ns ns Output pin slew fPIXCLK tPD t PFH t PLH tPFL tPLL CLOAD = 15pF Default Default Default Default Default Default PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 93 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Power on Reset (POR) Power on Reset (POR) Figure 37 shows the power on reset. Figure 37: Power On Reset >t2 Vtrig_rise Vtrig_fall DVDD t1 z (digital) t3 t1 t3 t1 Table 27: POR Characterization Symbol t1 t2 t3 t4 Typical 15.5s 0.4s 0.9s 2.0s 0.83Vs 1.07V Vtrig_rising Vtrig_falling PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 94 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Package Dimensions Package Dimensions Figure 38: D Seating plane A 1.250 0.125 48-Pin ILCC Package Outline Drawing 0.725 0.075 0.525 0.050 7.70 0.125 (For reference only) 1.40 First clear pixel 47X 0.80 48X 0.40 0.70 TYP 48 1 6.95 CTR C L 4.50 4.20 7.70 3.85 C L 0.70 TYP 10.000 0.075 6.95 C CTR L 4.284 CTR O0.15 A B C Lead finish: gold plating, 0.50 microns minimum thickness C L C 4.50 9.00 10.000 0.075 Substrate material: Plastic laminate Mold compound: Epoxy novolac 3.85 B 5.712 CTR O0.15 A B C Optical area Maximum rotation of optical area relative to package edges: 1 Maximum tilt of optical area relative to seating plane A : 25 microns relative to top of cover glass D : 50 microns Lid material: Borosilicate glass 0.40 thickness Image sensor die Note: All dimensions are in millimeters. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 95 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Revision History Revision History Rev C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/06 * Update Table 1, "Key Performance Parameters," on page 1 * Update Table 2, "Available Part Numbers," on page 1 * Update "General Description" on page 6 * Update Table 3, "Signal Description," on page 7 * Update Figure 1: "48-Pin ILCC 10x10 Package Pinout Diagram (Top View)," on page 8 * Update Figure 2: "Typical Configuration (connection)," on page 9 * Update Figure 3: "Block Diagram," on page 10 * Update "Pixel Array" on page 11 * Update "Default Readout Order" on page 12 * Update "Using Per-color or Global Gain Control" on page 13 * Update "Timing and Control" on page 13 * Update "SMIA Gain Model" on page 13 * Update "Micron Imaging Gain Model" on page 13 * Update Table 4, "Recommended Gain Settings," on page 14 * Update "Digital Gain" on page 14 * Update "PLL" on page 15 * Update Equation 6 on page 16 * Update "PLL Setup" on page 17 * Update "Readout Options" on page 17 * Update "Pixel Border" on page 18 * Update Figure 7: "8 Pixels in Normal and Column Mirror Readout Modes," on page 18 * Update "Programming Restrictions when Subsampling" on page 21 * Update "Shading Correction (SC)" on page 26 * Update "Output Data Timing (Parallel Pixel Data Interface)" on page 27 * Update Table 8, "Row Timing Parameters," on page 28 * Update "General Purpose Inputs" on page 29 * Update "Output Enable Control" on page 29 * Update Table 9, "Output Enable Control," on page 29 * Update Table 10, "Trigger Control," on page 30 * Update "Streaming/Standby Control" on page 30 * Update "Low Power Mode" on page 31 * Update "Slave Address/Data Direction Byte" on page 33 * Update "Two-Wire Serial Interface" on page 33 * Update "Registers" on page 37 * Update "Byte Ordering" on page 38 * Update "Bad Frames" on page 39 * Update Table 15, "SMIA Configuration," on page 42 * Update Table 16, "1: SMIA Parameter Limits," on page 44 * Update Table 17, "3: Manufacturer Specific," on page 46 * Update Table 18, "0: SMIA Configuration," on page 55 * Update Table 19, "1: SMIA Parameter Limits," on page 60 * Update Table 20, "3: Manufacturer Specific," on page 64 * Add "Electrical Specifications" on page 90 * Add Table 23, "Electrical Characteristics and Operating Conditions," on page 90 PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 96 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Preliminary MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor Revision History * * * * * * Add Table 24, "I/O Parameters," on page 92 Add Table 25, "Typical Power," on page 92 Add Table 26, "I/O Timing," on page 93 Add Figure 36: "I/O TIming," on page 93 Add Figure 37: "Power On Reset," on page 94 Add Table 27, "POR Characterization," on page 94 Rev B, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/06 * Update "Features" on page 1 * Update "General Description" on page 6 * Update Table 3, "Signal Description," on page 7 * Update "Typical Connections" on page 9 * Update Figure 3: "Block Diagram," on page 10 * Update "Sensor Core Description" on page 11 * Update "Analog Gain Options" on page 13 * Update "Gain Code Mapping" on page 14 * Update "Pedestal" on page 14 * Update "Integration Time" on page 14 * Update "PLL" on page 15 * Update Figure 7: "8 Pixels in Normal and Column Mirror Readout Modes," on page 18 * Update Figure 11: "Pixel Readout (no skipping, x_odd_inc=1, y_odd_inc=1)," on page 20 * Update "Programming Restrictions when Subsampling" on page 21 * Update Figure 19: "Pixel Data Timing Example," on page 27 * Update Table 8, "Row Timing Parameters," on page 28 * Update "General Purpose Inputs" on page 29 * Update "Output Enable Control" on page 29 * Update "Snapshot and Flash" on page 30 * Update Table 13, "Address Space Regions," on page 37 * Update "Register Notation" on page 37 * Update "Register Aliases" on page 37 * Update Table 15, "SMIA Configuration," on page 42 * Update Table 16, "1: SMIA Parameter Limits," on page 44 * Update Table 17, "3: Manufacturer Specific," on page 46 * Update Table 18, "0: SMIA Configuration," on page 55 * Update Table 19, "1: SMIA Parameter Limits," on page 60 * Update Table 20, "3: Manufacturer Specific," on page 64 * Add Figure 34: "CRA vs. Image Height," on page 87 * Add Figure 38: "48-Pin ILCC Package Outline Drawing," on page 95 Rev A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/06 * Initial release PDF: 09005aef8210fa55/Source: 09005aef8210f91a MT9E001__5.fm - Rev. C 10/06 EN 97 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. |
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